Core Register type definitions. More...

Topics
	Nested Vectored Interrupt Controller (NVIC)
	Type definitions for the NVIC Registers.

Data Structures
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...

union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...

union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...

union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...

Macros
#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U

#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U

#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

#define	SCB_NSACR_CP11_Pos 11U

#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

#define	SCB_NSACR_CP10_Pos 10U

#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

#define	SCB_NSACR_CPn_Pos 0U

#define	SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	SCB_ITCMCR_SZ_Pos 3U

#define	SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

#define	SCB_ITCMCR_RETEN_Pos 2U

#define	SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

#define	SCB_ITCMCR_RMW_Pos 1U

#define	SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

#define	SCB_ITCMCR_EN_Pos 0U

#define	SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/)

#define	SCB_DTCMCR_SZ_Pos 3U

#define	SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

#define	SCB_DTCMCR_RETEN_Pos 2U

#define	SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

#define	SCB_DTCMCR_RMW_Pos 1U

#define	SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

#define	SCB_DTCMCR_EN_Pos 0U

#define	SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/)

#define	SCB_AHBPCR_SZ_Pos 1U

#define	SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

#define	SCB_AHBPCR_EN_Pos 0U

#define	SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/)

#define	SCB_CACR_FORCEWT_Pos 2U

#define	SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

#define	SCB_CACR_ECCEN_Pos 1U

#define	SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

#define	SCB_CACR_SIWT_Pos 0U

#define	SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/)

#define	SCB_AHBSCR_INITCOUNT_Pos 11U

#define	SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

#define	SCB_AHBSCR_TPRI_Pos 2U

#define	SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

#define	SCB_AHBSCR_CTL_Pos 0U

#define	SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/)

#define	SCB_ABFSR_AXIMTYPE_Pos 8U

#define	SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

#define	SCB_ABFSR_EPPB_Pos 4U

#define	SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

#define	SCB_ABFSR_AXIM_Pos 3U

#define	SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

#define	SCB_ABFSR_AHBP_Pos 2U

#define	SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

#define	SCB_ABFSR_DTCM_Pos 1U

#define	SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

#define	SCB_ABFSR_ITCM_Pos 0U

#define	SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLBASE_Pos 29U

#define	SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	DWT_FUNCTION_ID_Pos 27U

#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

#define	DWT_FUNCTION_ACTION_Pos 4U

#define	DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)

#define	DWT_FUNCTION_MATCH_Pos 0U

#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

#define	EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

#define	EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

#define	EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

#define	EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

#define	EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

#define	EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

#define	EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

#define	EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

#define	DWT_FUNCTION_ID_Pos 27U

#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

#define	DWT_FUNCTION_ACTION_Pos 4U

#define	DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)

#define	DWT_FUNCTION_MATCH_Pos 0U

#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

#define	EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

#define	EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

#define	EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

#define	EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

#define	EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

#define	EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

#define	EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

#define	EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ACTLR_DISFOLD_Pos 2U

#define	SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

#define	SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

#define	SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_CYCDISS_Pos 23U

#define	DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

#define	DWT_FUNCTION_ID_Pos 27U

#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

#define	DWT_FUNCTION_ACTION_Pos 4U

#define	DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

#define	DWT_FUNCTION_MATCH_Pos 0U

#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_MASK_MASK_Pos 0U

#define	DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVADDR1_Pos 16U

#define	DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

#define	DWT_FUNCTION_DATAVADDR0_Pos 12U

#define	DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	DWT_FUNCTION_LNK1ENA_Pos 9U

#define	DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

#define	DWT_FUNCTION_DATAVMATCH_Pos 8U

#define	DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

#define	DWT_FUNCTION_CYCMATCH_Pos 7U

#define	DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

#define	DWT_FUNCTION_EMITRANGE_Pos 5U

#define	DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

#define	DWT_FUNCTION_FUNCTION_Pos 0U

#define	DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_MVFR2_VFP_Misc_Pos 4U

#define	FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	FPU_BASE (SCS_BASE + 0x0F30UL)

#define	FPU ((FPU_Type *) FPU_BASE )

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

#define	FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

#define	EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

#define	EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

#define	EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

#define	EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

#define	EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

#define	EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

#define	EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

#define	EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

#define	EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */

#define	EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */

#define	EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	APSR_N_Pos 31U

#define	APSR_N_Msk (1UL << APSR_N_Pos)

#define	APSR_Z_Pos 30U

#define	APSR_Z_Msk (1UL << APSR_Z_Pos)

#define	APSR_C_Pos 29U

#define	APSR_C_Msk (1UL << APSR_C_Pos)

#define	APSR_V_Pos 28U

#define	APSR_V_Msk (1UL << APSR_V_Pos)

#define	APSR_Q_Pos 27U

#define	APSR_Q_Msk (1UL << APSR_Q_Pos)

#define	IPSR_ISR_Pos 0U

#define	IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/)

#define	xPSR_N_Pos 31U

#define	xPSR_N_Msk (1UL << xPSR_N_Pos)

#define	xPSR_Z_Pos 30U

#define	xPSR_Z_Msk (1UL << xPSR_Z_Pos)

#define	xPSR_C_Pos 29U

#define	xPSR_C_Msk (1UL << xPSR_C_Pos)

#define	xPSR_V_Pos 28U

#define	xPSR_V_Msk (1UL << xPSR_V_Pos)

#define	xPSR_Q_Pos 27U

#define	xPSR_Q_Msk (1UL << xPSR_Q_Pos)

#define	xPSR_ICI_IT_2_Pos 25U

#define	xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)

#define	xPSR_T_Pos 24U

#define	xPSR_T_Msk (1UL << xPSR_T_Pos)

#define	xPSR_ICI_IT_1_Pos 10U

#define	xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)

#define	xPSR_ISR_Pos 0U

#define	xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/)

#define	CONTROL_SPSEL_Pos 1U

#define	CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

#define	CONTROL_nPRIV_Pos 0U

#define	CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/)

#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 4U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_DEVTYPE_SubType_Pos 0U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_MASK_MASK_Pos 0U

#define	DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVADDR1_Pos 16U

#define	DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

#define	DWT_FUNCTION_DATAVADDR0_Pos 12U

#define	DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	DWT_FUNCTION_LNK1ENA_Pos 9U

#define	DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

#define	DWT_FUNCTION_DATAVMATCH_Pos 8U

#define	DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

#define	DWT_FUNCTION_CYCMATCH_Pos 7U

#define	DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

#define	DWT_FUNCTION_EMITRANGE_Pos 5U

#define	DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

#define	DWT_FUNCTION_FUNCTION_Pos 0U

#define	DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos

#define	SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ACTLR_DISFOLD_Pos 2U

#define	SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

#define	SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

#define	SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_MASK_MASK_Pos 0U

#define	DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVADDR1_Pos 16U

#define	DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

#define	DWT_FUNCTION_DATAVADDR0_Pos 12U

#define	DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	DWT_FUNCTION_LNK1ENA_Pos 9U

#define	DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

#define	DWT_FUNCTION_DATAVMATCH_Pos 8U

#define	DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

#define	DWT_FUNCTION_CYCMATCH_Pos 7U

#define	DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

#define	DWT_FUNCTION_EMITRANGE_Pos 5U

#define	DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

#define	DWT_FUNCTION_FUNCTION_Pos 0U

#define	DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

#define	NVIC_STIR_INTID_Pos 0U

#define	NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11U

#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8U

#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0U

#define	SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8U

#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4U

#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1U

#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0U

#define	SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/)

#define	SCB_SHCSR_USGFAULTENA_Pos 18U

#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17U

#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16U

#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14U

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13U

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12U

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11U

#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10U

#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8U

#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7U

#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3U

#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1U

#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0U

#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/)

#define	SCB_CFSR_USGFAULTSR_Pos 16U

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8U

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0U

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/)

#define	SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

#define	SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

#define	SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

#define	SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

#define	SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

#define	SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

#define	SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

#define	SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

#define	SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

#define	SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/)

#define	SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

#define	SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

#define	SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

#define	SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

#define	SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

#define	SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

#define	SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

#define	SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

#define	SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

#define	SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

#define	SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

#define	SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

#define	SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

#define	SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

#define	SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

#define	SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

#define	SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

#define	SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

#define	SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

#define	SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

#define	SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

#define	SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

#define	SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31U

#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30U

#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1U

#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4U

#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3U

#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2U

#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1U

#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0U

#define	SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/)

#define	SCnSCB_ICTR_INTLINESNUM_Pos 0U

#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/)

#define	SCnSCB_ACTLR_DISFOLD_Pos 2U

#define	SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	ITM_TPR_PRIVMASK_Pos 0U

#define	ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/)

#define	ITM_TCR_BUSY_Pos 23U

#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_TraceBusID_Pos 16U

#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

#define	ITM_TCR_GTSFREQ_Pos 10U

#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

#define	ITM_TCR_TSPrescale_Pos 8U

#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4U

#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3U

#define	ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2U

#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1U

#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0U

#define	ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/)

#define	ITM_LSR_ByteAcc_Pos 2U

#define	ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1U

#define	ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0U

#define	ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/)

#define	DWT_CTRL_NUMCOMP_Pos 28U

#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

#define	DWT_CTRL_NOTRCPKT_Pos 27U

#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

#define	DWT_CTRL_NOEXTTRIG_Pos 26U

#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

#define	DWT_CTRL_NOCYCCNT_Pos 25U

#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

#define	DWT_CTRL_NOPRFCNT_Pos 24U

#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

#define	DWT_CTRL_CYCEVTENA_Pos 22U

#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

#define	DWT_CTRL_FOLDEVTENA_Pos 21U

#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

#define	DWT_CTRL_LSUEVTENA_Pos 20U

#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

#define	DWT_CTRL_SLEEPEVTENA_Pos 19U

#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

#define	DWT_CTRL_EXCEVTENA_Pos 18U

#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

#define	DWT_CTRL_CPIEVTENA_Pos 17U

#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

#define	DWT_CTRL_EXCTRCENA_Pos 16U

#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

#define	DWT_CTRL_PCSAMPLENA_Pos 12U

#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

#define	DWT_CTRL_SYNCTAP_Pos 10U

#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

#define	DWT_CTRL_CYCTAP_Pos 9U

#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

#define	DWT_CTRL_POSTINIT_Pos 5U

#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

#define	DWT_CTRL_POSTPRESET_Pos 1U

#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

#define	DWT_CTRL_CYCCNTENA_Pos 0U

#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/)

#define	DWT_CPICNT_CPICNT_Pos 0U

#define	DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/)

#define	DWT_EXCCNT_EXCCNT_Pos 0U

#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/)

#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0U

#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/)

#define	DWT_LSUCNT_LSUCNT_Pos 0U

#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/)

#define	DWT_FOLDCNT_FOLDCNT_Pos 0U

#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/)

#define	DWT_MASK_MASK_Pos 0U

#define	DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/)

#define	DWT_FUNCTION_MATCHED_Pos 24U

#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

#define	DWT_FUNCTION_DATAVADDR1_Pos 16U

#define	DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

#define	DWT_FUNCTION_DATAVADDR0_Pos 12U

#define	DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

#define	DWT_FUNCTION_DATAVSIZE_Pos 10U

#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

#define	DWT_FUNCTION_LNK1ENA_Pos 9U

#define	DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

#define	DWT_FUNCTION_DATAVMATCH_Pos 8U

#define	DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

#define	DWT_FUNCTION_CYCMATCH_Pos 7U

#define	DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

#define	DWT_FUNCTION_EMITRANGE_Pos 5U

#define	DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

#define	DWT_FUNCTION_FUNCTION_Pos 0U

#define	DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16U

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25U

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19U

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18U

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17U

#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16U

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3U

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2U

#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1U

#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/)

#define	CoreDebug_DCRSR_REGWnR_Pos 16U

#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0U

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/)

#define	CoreDebug_DEMCR_TRCENA_Pos 24U

#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19U

#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18U

#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17U

#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16U

#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10U

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9U

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8U

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7U

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6U

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4U

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0U

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	ITM_BASE (0xE0000000UL)

#define	DWT_BASE (0xE0001000UL)

#define	TPI_BASE (0xE0040000UL)

#define	CoreDebug_BASE (0xE000EDF0UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	ITM ((ITM_Type *) ITM_BASE )

#define	DWT ((DWT_Type *) DWT_BASE )

#define	TPI ((TPI_Type *) TPI_BASE )

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

#define	NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

#define	NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_GetActive __NVIC_GetActive

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

#define	SCB_CPUID_IMPLEMENTER_Pos 24U

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20U

#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_ARCHITECTURE_Pos 16U

#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

#define	SCB_CPUID_PARTNO_Pos 4U

#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0U

#define	SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/)

#define	SCB_ICSR_NMIPENDSET_Pos 31U

#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28U

#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27U

#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26U

#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25U

#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23U

#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22U

#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12U

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0U

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/)

#define	SCB_VTOR_TBLOFF_Pos 7U

#define	SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16U

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16U

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15U

#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2U

#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1U

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4U

#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2U

#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1U

#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9U

#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3U

#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15U

#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0U

#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/)

#define	SysTick_CTRL_COUNTFLAG_Pos 16U

#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2U

#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1U

#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0U

#define	SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/)

#define	SysTick_LOAD_RELOAD_Pos 0U

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/)

#define	SysTick_VAL_CURRENT_Pos 0U

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/)

#define	SysTick_CALIB_NOREF_Pos 31U

#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30U

#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0U

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/)

#define	_VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
	Mask and shift a bit field value for use in a register bit range.

#define	_FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
	Mask and shift a register value to extract a bit filed value.

#define	SCS_BASE (0xE000E000UL)

#define	SysTick_BASE (SCS_BASE + 0x0010UL)

#define	NVIC_BASE (SCS_BASE + 0x0100UL)

#define	SCB_BASE (SCS_BASE + 0x0D00UL)

#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )

#define	SCB ((SCB_Type *) SCB_BASE )

#define	SysTick ((SysTick_Type *) SysTick_BASE )

#define	NVIC ((NVIC_Type *) NVIC_BASE )

#define	NVIC_EnableIRQ __NVIC_EnableIRQ

#define	NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

#define	NVIC_DisableIRQ __NVIC_DisableIRQ

#define	NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

#define	NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

#define	NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

#define	NVIC_SetPriority __NVIC_SetPriority

#define	NVIC_GetPriority __NVIC_GetPriority

#define	NVIC_SystemReset __NVIC_SystemReset

#define	NVIC_SetVector __NVIC_SetVector

#define	NVIC_GetVector __NVIC_GetVector

#define	NVIC_USER_IRQ_OFFSET 16

#define	EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

#define	EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

#define	EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	APSR_GE_Pos 16U

#define	APSR_GE_Msk (0xFUL << APSR_GE_Pos)

#define	xPSR_GE_Pos 16U

#define	xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)

#define	CONTROL_FPCA_Pos 2U

#define	CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	SCB_ITCMCR_SZ_Pos 3U

#define	SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

#define	SCB_ITCMCR_RETEN_Pos 2U

#define	SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

#define	SCB_ITCMCR_RMW_Pos 1U

#define	SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

#define	SCB_ITCMCR_EN_Pos 0U

#define	SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/)

#define	SCB_DTCMCR_SZ_Pos 3U

#define	SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

#define	SCB_DTCMCR_RETEN_Pos 2U

#define	SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

#define	SCB_DTCMCR_RMW_Pos 1U

#define	SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

#define	SCB_DTCMCR_EN_Pos 0U

#define	SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/)

#define	SCB_AHBPCR_SZ_Pos 1U

#define	SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

#define	SCB_AHBPCR_EN_Pos 0U

#define	SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/)

#define	SCB_CACR_FORCEWT_Pos 2U

#define	SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

#define	SCB_CACR_ECCEN_Pos 1U

#define	SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

#define	SCB_CACR_SIWT_Pos 0U

#define	SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/)

#define	SCB_AHBSCR_INITCOUNT_Pos 11U

#define	SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

#define	SCB_AHBSCR_TPRI_Pos 2U

#define	SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

#define	SCB_AHBSCR_CTL_Pos 0U

#define	SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/)

#define	SCB_ABFSR_AXIMTYPE_Pos 8U

#define	SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

#define	SCB_ABFSR_EPPB_Pos 4U

#define	SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

#define	SCB_ABFSR_AXIM_Pos 3U

#define	SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

#define	SCB_ABFSR_AHBP_Pos 2U

#define	SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

#define	SCB_ABFSR_DTCM_Pos 1U

#define	SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

#define	SCB_ABFSR_ITCM_Pos 0U

#define	SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_BASE (SCS_BASE + 0x0F30UL)

#define	FPU ((FPU_Type *) FPU_BASE )

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_BASE (SCS_BASE + 0x0F30UL)

#define	FPU ((FPU_Type *) FPU_BASE )

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_BASE (SCS_BASE + 0x0F30UL)

#define	FPU ((FPU_Type *) FPU_BASE )

#define	SCB_CCR_BP_Pos 18U

#define	SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

#define	SCB_CCR_IC_Pos 17U

#define	SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)

#define	SCB_CCR_DC_Pos 16U

#define	SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)

#define	SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	SCB_CLIDR_LOUU_Pos 27U

#define	SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

#define	SCB_CLIDR_LOC_Pos 24U

#define	SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

#define	SCB_CTR_FORMAT_Pos 29U

#define	SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

#define	SCB_CTR_CWG_Pos 24U

#define	SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

#define	SCB_CTR_ERG_Pos 20U

#define	SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

#define	SCB_CTR_DMINLINE_Pos 16U

#define	SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

#define	SCB_CTR_IMINLINE_Pos 0U

#define	SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/)

#define	SCB_CCSIDR_WT_Pos 31U

#define	SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

#define	SCB_CCSIDR_WB_Pos 30U

#define	SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

#define	SCB_CCSIDR_RA_Pos 29U

#define	SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

#define	SCB_CCSIDR_WA_Pos 28U

#define	SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

#define	SCB_CCSIDR_NUMSETS_Pos 13U

#define	SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

#define	SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

#define	SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

#define	SCB_CCSIDR_LINESIZE_Pos 0U

#define	SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/)

#define	SCB_CSSELR_LEVEL_Pos 1U

#define	SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

#define	SCB_CSSELR_IND_Pos 0U

#define	SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/)

#define	SCB_STIR_INTID_Pos 0U

#define	SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/)

#define	SCB_DCISW_WAY_Pos 30U

#define	SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

#define	SCB_DCISW_SET_Pos 5U

#define	SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

#define	SCB_DCCSW_WAY_Pos 30U

#define	SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

#define	SCB_DCCSW_SET_Pos 5U

#define	SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

#define	SCB_DCCISW_WAY_Pos 30U

#define	SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

#define	SCB_DCCISW_SET_Pos 5U

#define	SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_BASE (SCS_BASE + 0x0F30UL)

#define	FPU ((FPU_Type *) FPU_BASE )

#define	SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

#define	SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

#define	SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

#define	SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

#define	FPU_FPCCR_ASPEN_Pos 31U

#define	FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

#define	FPU_FPCCR_LSPEN_Pos 30U

#define	FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

#define	FPU_FPCCR_MONRDY_Pos 8U

#define	FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

#define	FPU_FPCCR_BFRDY_Pos 6U

#define	FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

#define	FPU_FPCCR_MMRDY_Pos 5U

#define	FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

#define	FPU_FPCCR_HFRDY_Pos 4U

#define	FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

#define	FPU_FPCCR_THREAD_Pos 3U

#define	FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

#define	FPU_FPCCR_USER_Pos 1U

#define	FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

#define	FPU_FPCCR_LSPACT_Pos 0U

#define	FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/)

#define	FPU_FPCAR_ADDRESS_Pos 3U

#define	FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

#define	FPU_FPDSCR_AHP_Pos 26U

#define	FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

#define	FPU_FPDSCR_DN_Pos 25U

#define	FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

#define	FPU_FPDSCR_FZ_Pos 24U

#define	FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

#define	FPU_FPDSCR_RMode_Pos 22U

#define	FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

#define	FPU_MVFR0_FP_rounding_modes_Pos 28U

#define	FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

#define	FPU_MVFR0_Short_vectors_Pos 24U

#define	FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

#define	FPU_MVFR0_Square_root_Pos 20U

#define	FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

#define	FPU_MVFR0_Divide_Pos 16U

#define	FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

#define	FPU_MVFR0_FP_excep_trapping_Pos 12U

#define	FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

#define	FPU_MVFR0_Double_precision_Pos 8U

#define	FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

#define	FPU_MVFR0_Single_precision_Pos 4U

#define	FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

#define	FPU_MVFR0_A_SIMD_registers_Pos 0U

#define	FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/)

#define	FPU_MVFR1_FP_fused_MAC_Pos 28U

#define	FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

#define	FPU_MVFR1_FP_HPFP_Pos 24U

#define	FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

#define	FPU_MVFR1_D_NaN_mode_Pos 4U

#define	FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

#define	FPU_MVFR1_FtZ_mode_Pos 0U

#define	FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/)

#define	FPU_MVFR2_VFP_Misc_Pos 4U

#define	FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

#define	FPU_BASE (SCS_BASE + 0x0F30UL)

#define	FPU ((FPU_Type *) FPU_BASE )

#define	EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */

#define	EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */

#define	EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	xPSR_IT_Pos 25U

#define	xPSR_IT_Msk (3UL << xPSR_IT_Pos)

#define	CONTROL_SFPA_Pos 3U

#define	CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U

#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U

#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

#define	SCB_NSACR_CP11_Pos 11U

#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

#define	SCB_NSACR_CP10_Pos 10U

#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

#define	SCB_NSACR_CPn_Pos 0U

#define	SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	DWT_CTRL_CYCDISS_Pos 23U

#define	DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

#define	DWT_FUNCTION_ID_Pos 27U

#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

#define	DWT_FUNCTION_ACTION_Pos 4U

#define	DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

#define	DWT_FUNCTION_MATCH_Pos 0U

#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U

#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U

#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

#define	SCB_NSACR_CP11_Pos 11U

#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

#define	SCB_NSACR_CP10_Pos 10U

#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

#define	SCB_NSACR_CPn_Pos 0U

#define	SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	DWT_CTRL_CYCDISS_Pos 23U

#define	DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

#define	DWT_FUNCTION_ID_Pos 27U

#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

#define	DWT_FUNCTION_ACTION_Pos 4U

#define	DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

#define	DWT_FUNCTION_MATCH_Pos 0U

#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

#define	EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

#define	EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

#define	EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

#define	EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

#define	EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

#define	EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

#define	EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

#define	EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

#define	SCB_ICSR_PENDNMISET_Pos 31U

#define	SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

#define	SCB_ICSR_PENDNMICLR_Pos 30U

#define	SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

#define	SCB_ICSR_STTNS_Pos 24U

#define	SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

#define	SCB_AIRCR_PRIS_Pos 14U

#define	SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

#define	SCB_AIRCR_BFHFNMINS_Pos 13U

#define	SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

#define	SCB_AIRCR_SYSRESETREQS_Pos 3U

#define	SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

#define	SCB_SCR_SLEEPDEEPS_Pos 3U

#define	SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

#define	SCB_CCR_STKOFHFNMIGN_Pos 10U

#define	SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

#define	SCB_SHCSR_HARDFAULTPENDED_Pos 21U

#define	SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

#define	SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

#define	SCB_SHCSR_SECUREFAULTENA_Pos 19U

#define	SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

#define	SCB_SHCSR_NMIACT_Pos 5U

#define	SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

#define	SCB_SHCSR_SECUREFAULTACT_Pos 4U

#define	SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

#define	SCB_SHCSR_HARDFAULTACT_Pos 2U

#define	SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

#define	SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

#define	SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

#define	SCB_NSACR_CP11_Pos 11U

#define	SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

#define	SCB_NSACR_CP10_Pos 10U

#define	SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

#define	SCB_NSACR_CPn_Pos 0U

#define	SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/)

#define	ITM_STIM_DISABLED_Pos 1U

#define	ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

#define	ITM_STIM_FIFOREADY_Pos 0U

#define	ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/)

#define	ITM_TCR_TRACEBUSID_Pos 16U

#define	ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

#define	ITM_TCR_TSPRESCALE_Pos 8U

#define	ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

#define	ITM_TCR_STALLENA_Pos 5U

#define	ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

#define	DWT_CTRL_CYCDISS_Pos 23U

#define	DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

#define	DWT_FUNCTION_ID_Pos 27U

#define	DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

#define	DWT_FUNCTION_ACTION_Pos 4U

#define	DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

#define	DWT_FUNCTION_MATCH_Pos 0U

#define	DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	FPU_FPCCR_LSPENS_Pos 29U

#define	FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

#define	FPU_FPCCR_CLRONRET_Pos 28U

#define	FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

#define	FPU_FPCCR_CLRONRETS_Pos 27U

#define	FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

#define	FPU_FPCCR_TS_Pos 26U

#define	FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

#define	FPU_FPCCR_UFRDY_Pos 10U

#define	FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

#define	FPU_FPCCR_SPLIMVIOL_Pos 9U

#define	FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

#define	FPU_FPCCR_SFRDY_Pos 7U

#define	FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

#define	FPU_FPCCR_S_Pos 2U

#define	FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

#define	CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

#define	CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

#define	CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

#define	CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

#define	CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

#define	CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/)

#define	CoreDebug_DSCSR_CDS_Pos 16U

#define	CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

#define	CoreDebug_DSCSR_SBRSEL_Pos 1U

#define	CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

#define	CoreDebug_DSCSR_SBRSELEN_Pos 0U

#define	CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/)

#define	FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

#define	EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

#define	EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

#define	EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

#define	EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

#define	EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

#define	EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

#define	EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

#define	EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

Detailed Description

Core Register type definitions.

Macro Definition Documentation

◆ _FLD2VAL [1/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 2021 of file core_armv81mml.h.

◆ _FLD2VAL [2/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1100 of file core_armv8mbl.h.

◆ _FLD2VAL [3/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1865 of file core_armv8mml.h.

◆ _FLD2VAL [4/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 521 of file core_cm0.h.

◆ _FLD2VAL [5/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 635 of file core_cm0plus.h.

◆ _FLD2VAL [6/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 547 of file core_cm1.h.

◆ _FLD2VAL [7/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1175 of file core_cm23.h.

◆ _FLD2VAL [8/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1362 of file core_cm3.h.

◆ _FLD2VAL [9/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1940 of file core_cm33.h.

◆ _FLD2VAL [10/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1940 of file core_cm35p.h.

◆ _FLD2VAL [11/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1532 of file core_cm4.h.

◆ _FLD2VAL [12/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1755 of file core_cm7.h.

◆ _FLD2VAL [13/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 644 of file core_sc000.h.

◆ _FLD2VAL [14/14]

#define _FLD2VAL	(		field,
			value ) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)

Mask and shift a register value to extract a bit filed value.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of register. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted bit field value.

Definition at line 1345 of file core_sc300.h.

◆ _VAL2FLD [1/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 2013 of file core_armv81mml.h.

◆ _VAL2FLD [2/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1092 of file core_armv8mbl.h.

◆ _VAL2FLD [3/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1857 of file core_armv8mml.h.

◆ _VAL2FLD [4/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 513 of file core_cm0.h.

◆ _VAL2FLD [5/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 627 of file core_cm0plus.h.

◆ _VAL2FLD [6/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 539 of file core_cm1.h.

◆ _VAL2FLD [7/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1167 of file core_cm23.h.

◆ _VAL2FLD [8/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1354 of file core_cm3.h.

◆ _VAL2FLD [9/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1932 of file core_cm33.h.

◆ _VAL2FLD [10/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1932 of file core_cm35p.h.

◆ _VAL2FLD [11/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1524 of file core_cm4.h.

◆ _VAL2FLD [12/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1747 of file core_cm7.h.

◆ _VAL2FLD [13/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 636 of file core_sc000.h.

◆ _VAL2FLD [14/14]

#define _VAL2FLD	(		field,
			value ) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)

Mask and shift a bit field value for use in a register bit range.

Parameters

[in]	field	Name of the register bit field.
[in]	value	Value of the bit field. This parameter is interpreted as an uint32_t type.

Returns: Masked and shifted value.

Definition at line 1337 of file core_sc300.h.

◆ APSR_C_Msk [1/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 339 of file core_armv81mml.h.

◆ APSR_C_Msk [2/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file core_armv8mbl.h.

◆ APSR_C_Msk [3/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file core_armv8mml.h.

◆ APSR_C_Msk [4/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file core_cm0.h.

◆ APSR_C_Msk [5/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 231 of file core_cm0plus.h.

◆ APSR_C_Msk [6/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 220 of file core_cm1.h.

◆ APSR_C_Msk [7/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 254 of file core_cm23.h.

◆ APSR_C_Msk [8/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file core_cm3.h.

◆ APSR_C_Msk [9/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file core_cm33.h.

◆ APSR_C_Msk [10/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 338 of file core_cm35p.h.

◆ APSR_C_Msk [11/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 283 of file core_cm4.h.

◆ APSR_C_Msk [12/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 298 of file core_cm7.h.

◆ APSR_C_Msk [13/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 226 of file core_sc000.h.

◆ APSR_C_Msk [14/14]

#define APSR_C_Msk (1UL << APSR_C_Pos)

APSR: C Mask

Definition at line 228 of file core_sc300.h.

◆ APSR_C_Pos [1/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 338 of file core_armv81mml.h.

◆ APSR_C_Pos [2/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file core_armv8mbl.h.

◆ APSR_C_Pos [3/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file core_armv8mml.h.

◆ APSR_C_Pos [4/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file core_cm0.h.

◆ APSR_C_Pos [5/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 230 of file core_cm0plus.h.

◆ APSR_C_Pos [6/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 219 of file core_cm1.h.

◆ APSR_C_Pos [7/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 253 of file core_cm23.h.

◆ APSR_C_Pos [8/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file core_cm3.h.

◆ APSR_C_Pos [9/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file core_cm33.h.

◆ APSR_C_Pos [10/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 337 of file core_cm35p.h.

◆ APSR_C_Pos [11/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 282 of file core_cm4.h.

◆ APSR_C_Pos [12/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 297 of file core_cm7.h.

◆ APSR_C_Pos [13/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 225 of file core_sc000.h.

◆ APSR_C_Pos [14/14]

#define APSR_C_Pos 29U

APSR: C Position

Definition at line 227 of file core_sc300.h.

◆ APSR_GE_Msk [1/6]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 348 of file core_armv81mml.h.

◆ APSR_GE_Msk [2/6]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file core_armv8mml.h.

◆ APSR_GE_Msk [3/6]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file core_cm33.h.

◆ APSR_GE_Msk [4/6]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 347 of file core_cm35p.h.

◆ APSR_GE_Msk [5/6]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 292 of file core_cm4.h.

◆ APSR_GE_Msk [6/6]

#define APSR_GE_Msk (0xFUL << APSR_GE_Pos)

APSR: GE Mask

Definition at line 307 of file core_cm7.h.

◆ APSR_GE_Pos [1/6]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 347 of file core_armv81mml.h.

◆ APSR_GE_Pos [2/6]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file core_armv8mml.h.

◆ APSR_GE_Pos [3/6]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file core_cm33.h.

◆ APSR_GE_Pos [4/6]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 346 of file core_cm35p.h.

◆ APSR_GE_Pos [5/6]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 291 of file core_cm4.h.

◆ APSR_GE_Pos [6/6]

#define APSR_GE_Pos 16U

APSR: GE Position

Definition at line 306 of file core_cm7.h.

◆ APSR_N_Msk [1/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 333 of file core_armv81mml.h.

◆ APSR_N_Msk [2/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file core_armv8mbl.h.

◆ APSR_N_Msk [3/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file core_armv8mml.h.

◆ APSR_N_Msk [4/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file core_cm0.h.

◆ APSR_N_Msk [5/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 225 of file core_cm0plus.h.

◆ APSR_N_Msk [6/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 214 of file core_cm1.h.

◆ APSR_N_Msk [7/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 248 of file core_cm23.h.

◆ APSR_N_Msk [8/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file core_cm3.h.

◆ APSR_N_Msk [9/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file core_cm33.h.

◆ APSR_N_Msk [10/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 332 of file core_cm35p.h.

◆ APSR_N_Msk [11/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 277 of file core_cm4.h.

◆ APSR_N_Msk [12/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 292 of file core_cm7.h.

◆ APSR_N_Msk [13/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 220 of file core_sc000.h.

◆ APSR_N_Msk [14/14]

#define APSR_N_Msk (1UL << APSR_N_Pos)

APSR: N Mask

Definition at line 222 of file core_sc300.h.

◆ APSR_N_Pos [1/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 332 of file core_armv81mml.h.

◆ APSR_N_Pos [2/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file core_armv8mbl.h.

◆ APSR_N_Pos [3/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file core_armv8mml.h.

◆ APSR_N_Pos [4/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file core_cm0.h.

◆ APSR_N_Pos [5/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 224 of file core_cm0plus.h.

◆ APSR_N_Pos [6/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 213 of file core_cm1.h.

◆ APSR_N_Pos [7/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 247 of file core_cm23.h.

◆ APSR_N_Pos [8/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file core_cm3.h.

◆ APSR_N_Pos [9/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file core_cm33.h.

◆ APSR_N_Pos [10/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 331 of file core_cm35p.h.

◆ APSR_N_Pos [11/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 276 of file core_cm4.h.

◆ APSR_N_Pos [12/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 291 of file core_cm7.h.

◆ APSR_N_Pos [13/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 219 of file core_sc000.h.

◆ APSR_N_Pos [14/14]

#define APSR_N_Pos 31U

APSR: N Position

Definition at line 221 of file core_sc300.h.

◆ APSR_Q_Msk [1/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 345 of file core_armv81mml.h.

◆ APSR_Q_Msk [2/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file core_armv8mml.h.

◆ APSR_Q_Msk [3/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file core_cm3.h.

◆ APSR_Q_Msk [4/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file core_cm33.h.

◆ APSR_Q_Msk [5/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 344 of file core_cm35p.h.

◆ APSR_Q_Msk [6/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 289 of file core_cm4.h.

◆ APSR_Q_Msk [7/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 304 of file core_cm7.h.

◆ APSR_Q_Msk [8/8]

#define APSR_Q_Msk (1UL << APSR_Q_Pos)

APSR: Q Mask

Definition at line 234 of file core_sc300.h.

◆ APSR_Q_Pos [1/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 344 of file core_armv81mml.h.

◆ APSR_Q_Pos [2/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file core_armv8mml.h.

◆ APSR_Q_Pos [3/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file core_cm3.h.

◆ APSR_Q_Pos [4/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file core_cm33.h.

◆ APSR_Q_Pos [5/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 343 of file core_cm35p.h.

◆ APSR_Q_Pos [6/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 288 of file core_cm4.h.

◆ APSR_Q_Pos [7/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 303 of file core_cm7.h.

◆ APSR_Q_Pos [8/8]

#define APSR_Q_Pos 27U

APSR: Q Position

Definition at line 233 of file core_sc300.h.

◆ APSR_V_Msk [1/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 342 of file core_armv81mml.h.

◆ APSR_V_Msk [2/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file core_armv8mbl.h.

◆ APSR_V_Msk [3/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file core_armv8mml.h.

◆ APSR_V_Msk [4/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file core_cm0.h.

◆ APSR_V_Msk [5/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 234 of file core_cm0plus.h.

◆ APSR_V_Msk [6/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 223 of file core_cm1.h.

◆ APSR_V_Msk [7/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 257 of file core_cm23.h.

◆ APSR_V_Msk [8/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file core_cm3.h.

◆ APSR_V_Msk [9/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file core_cm33.h.

◆ APSR_V_Msk [10/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 341 of file core_cm35p.h.

◆ APSR_V_Msk [11/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 286 of file core_cm4.h.

◆ APSR_V_Msk [12/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 301 of file core_cm7.h.

◆ APSR_V_Msk [13/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 229 of file core_sc000.h.

◆ APSR_V_Msk [14/14]

#define APSR_V_Msk (1UL << APSR_V_Pos)

APSR: V Mask

Definition at line 231 of file core_sc300.h.

◆ APSR_V_Pos [1/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 341 of file core_armv81mml.h.

◆ APSR_V_Pos [2/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file core_armv8mbl.h.

◆ APSR_V_Pos [3/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file core_armv8mml.h.

◆ APSR_V_Pos [4/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file core_cm0.h.

◆ APSR_V_Pos [5/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 233 of file core_cm0plus.h.

◆ APSR_V_Pos [6/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 222 of file core_cm1.h.

◆ APSR_V_Pos [7/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 256 of file core_cm23.h.

◆ APSR_V_Pos [8/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file core_cm3.h.

◆ APSR_V_Pos [9/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file core_cm33.h.

◆ APSR_V_Pos [10/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 340 of file core_cm35p.h.

◆ APSR_V_Pos [11/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 285 of file core_cm4.h.

◆ APSR_V_Pos [12/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 300 of file core_cm7.h.

◆ APSR_V_Pos [13/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 228 of file core_sc000.h.

◆ APSR_V_Pos [14/14]

#define APSR_V_Pos 28U

APSR: V Position

Definition at line 230 of file core_sc300.h.

◆ APSR_Z_Msk [1/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 336 of file core_armv81mml.h.

◆ APSR_Z_Msk [2/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 251 of file core_armv8mbl.h.

◆ APSR_Z_Msk [3/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 335 of file core_armv8mml.h.

◆ APSR_Z_Msk [4/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 217 of file core_cm0.h.

◆ APSR_Z_Msk [5/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 228 of file core_cm0plus.h.

◆ APSR_Z_Msk [6/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 217 of file core_cm1.h.

◆ APSR_Z_Msk [7/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 251 of file core_cm23.h.

◆ APSR_Z_Msk [8/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 225 of file core_cm3.h.

◆ APSR_Z_Msk [9/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 335 of file core_cm33.h.

◆ APSR_Z_Msk [10/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 335 of file core_cm35p.h.

◆ APSR_Z_Msk [11/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 280 of file core_cm4.h.

◆ APSR_Z_Msk [12/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 295 of file core_cm7.h.

◆ APSR_Z_Msk [13/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 223 of file core_sc000.h.

◆ APSR_Z_Msk [14/14]

#define APSR_Z_Msk (1UL << APSR_Z_Pos)

APSR: Z Mask

Definition at line 225 of file core_sc300.h.

◆ APSR_Z_Pos [1/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 335 of file core_armv81mml.h.

◆ APSR_Z_Pos [2/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 250 of file core_armv8mbl.h.

◆ APSR_Z_Pos [3/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 334 of file core_armv8mml.h.

◆ APSR_Z_Pos [4/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 216 of file core_cm0.h.

◆ APSR_Z_Pos [5/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 227 of file core_cm0plus.h.

◆ APSR_Z_Pos [6/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 216 of file core_cm1.h.

◆ APSR_Z_Pos [7/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 250 of file core_cm23.h.

◆ APSR_Z_Pos [8/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 224 of file core_cm3.h.

◆ APSR_Z_Pos [9/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 334 of file core_cm33.h.

◆ APSR_Z_Pos [10/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 334 of file core_cm35p.h.

◆ APSR_Z_Pos [11/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 279 of file core_cm4.h.

◆ APSR_Z_Pos [12/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 294 of file core_cm7.h.

◆ APSR_Z_Pos [13/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 222 of file core_sc000.h.

◆ APSR_Z_Pos [14/14]

#define APSR_Z_Pos 30U

APSR: Z Position

Definition at line 224 of file core_sc300.h.

◆ CONTROL_FPCA_Msk [1/6]

#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

Definition at line 441 of file core_armv81mml.h.

◆ CONTROL_FPCA_Msk [2/6]

#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

Definition at line 440 of file core_armv8mml.h.

◆ CONTROL_FPCA_Msk [3/6]

#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

Definition at line 440 of file core_cm33.h.

◆ CONTROL_FPCA_Msk [4/6]

#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

Definition at line 440 of file core_cm35p.h.

◆ CONTROL_FPCA_Msk [5/6]

#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

Definition at line 385 of file core_cm4.h.

◆ CONTROL_FPCA_Msk [6/6]

#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)

CONTROL: FPCA Mask

Definition at line 400 of file core_cm7.h.

◆ CONTROL_FPCA_Pos [1/6]

#define CONTROL_FPCA_Pos 2U

CONTROL: FPCA Position

Definition at line 440 of file core_armv81mml.h.

◆ CONTROL_FPCA_Pos [2/6]

#define CONTROL_FPCA_Pos 2U

CONTROL: FPCA Position

Definition at line 439 of file core_armv8mml.h.

◆ CONTROL_FPCA_Pos [3/6]

#define CONTROL_FPCA_Pos 2U

CONTROL: FPCA Position

Definition at line 439 of file core_cm33.h.

◆ CONTROL_FPCA_Pos [4/6]

#define CONTROL_FPCA_Pos 2U

CONTROL: FPCA Position

Definition at line 439 of file core_cm35p.h.

◆ CONTROL_FPCA_Pos [5/6]

#define CONTROL_FPCA_Pos 2U

CONTROL: FPCA Position

Definition at line 384 of file core_cm4.h.

◆ CONTROL_FPCA_Pos [6/6]

#define CONTROL_FPCA_Pos 2U

CONTROL: FPCA Position

Definition at line 399 of file core_cm7.h.

◆ CONTROL_nPRIV_Msk [1/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 447 of file core_armv81mml.h.

◆ CONTROL_nPRIV_Msk [2/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 336 of file core_armv8mbl.h.

◆ CONTROL_nPRIV_Msk [3/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 446 of file core_armv8mml.h.

◆ CONTROL_nPRIV_Msk [4/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 313 of file core_cm0plus.h.

◆ CONTROL_nPRIV_Msk [5/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 336 of file core_cm23.h.

◆ CONTROL_nPRIV_Msk [6/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 325 of file core_cm3.h.

◆ CONTROL_nPRIV_Msk [7/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 446 of file core_cm33.h.

◆ CONTROL_nPRIV_Msk [8/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 446 of file core_cm35p.h.

◆ CONTROL_nPRIV_Msk [9/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 391 of file core_cm4.h.

◆ CONTROL_nPRIV_Msk [10/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 406 of file core_cm7.h.

◆ CONTROL_nPRIV_Msk [11/11]

#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)

CONTROL: nPRIV Mask

Definition at line 325 of file core_sc300.h.

◆ CONTROL_nPRIV_Pos [1/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 446 of file core_armv81mml.h.

◆ CONTROL_nPRIV_Pos [2/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 335 of file core_armv8mbl.h.

◆ CONTROL_nPRIV_Pos [3/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 445 of file core_armv8mml.h.

◆ CONTROL_nPRIV_Pos [4/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 312 of file core_cm0plus.h.

◆ CONTROL_nPRIV_Pos [5/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 335 of file core_cm23.h.

◆ CONTROL_nPRIV_Pos [6/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 324 of file core_cm3.h.

◆ CONTROL_nPRIV_Pos [7/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 445 of file core_cm33.h.

◆ CONTROL_nPRIV_Pos [8/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 445 of file core_cm35p.h.

◆ CONTROL_nPRIV_Pos [9/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 390 of file core_cm4.h.

◆ CONTROL_nPRIV_Pos [10/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 405 of file core_cm7.h.

◆ CONTROL_nPRIV_Pos [11/11]

#define CONTROL_nPRIV_Pos 0U

CONTROL: nPRIV Position

Definition at line 324 of file core_sc300.h.

◆ CONTROL_SFPA_Msk [1/4]

#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

CONTROL: SFPA Mask

Definition at line 438 of file core_armv81mml.h.

◆ CONTROL_SFPA_Msk [2/4]

#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

CONTROL: SFPA Mask

Definition at line 437 of file core_armv8mml.h.

◆ CONTROL_SFPA_Msk [3/4]

#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

CONTROL: SFPA Mask

Definition at line 437 of file core_cm33.h.

◆ CONTROL_SFPA_Msk [4/4]

#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)

CONTROL: SFPA Mask

Definition at line 437 of file core_cm35p.h.

◆ CONTROL_SFPA_Pos [1/4]

#define CONTROL_SFPA_Pos 3U

CONTROL: SFPA Position

Definition at line 437 of file core_armv81mml.h.

◆ CONTROL_SFPA_Pos [2/4]

#define CONTROL_SFPA_Pos 3U

CONTROL: SFPA Position

Definition at line 436 of file core_armv8mml.h.

◆ CONTROL_SFPA_Pos [3/4]

#define CONTROL_SFPA_Pos 3U

CONTROL: SFPA Position

Definition at line 436 of file core_cm33.h.

◆ CONTROL_SFPA_Pos [4/4]

#define CONTROL_SFPA_Pos 3U

CONTROL: SFPA Position

Definition at line 436 of file core_cm35p.h.

◆ CONTROL_SPSEL_Msk [1/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 444 of file core_armv81mml.h.

◆ CONTROL_SPSEL_Msk [2/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 333 of file core_armv8mbl.h.

◆ CONTROL_SPSEL_Msk [3/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 443 of file core_armv8mml.h.

◆ CONTROL_SPSEL_Msk [4/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 299 of file core_cm0.h.

◆ CONTROL_SPSEL_Msk [5/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 310 of file core_cm0plus.h.

◆ CONTROL_SPSEL_Msk [6/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 299 of file core_cm1.h.

◆ CONTROL_SPSEL_Msk [7/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 333 of file core_cm23.h.

◆ CONTROL_SPSEL_Msk [8/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 322 of file core_cm3.h.

◆ CONTROL_SPSEL_Msk [9/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 443 of file core_cm33.h.

◆ CONTROL_SPSEL_Msk [10/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 443 of file core_cm35p.h.

◆ CONTROL_SPSEL_Msk [11/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 388 of file core_cm4.h.

◆ CONTROL_SPSEL_Msk [12/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 403 of file core_cm7.h.

◆ CONTROL_SPSEL_Msk [13/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 305 of file core_sc000.h.

◆ CONTROL_SPSEL_Msk [14/14]

#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)

CONTROL: SPSEL Mask

Definition at line 322 of file core_sc300.h.

◆ CONTROL_SPSEL_Pos [1/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 443 of file core_armv81mml.h.

◆ CONTROL_SPSEL_Pos [2/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 332 of file core_armv8mbl.h.

◆ CONTROL_SPSEL_Pos [3/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 442 of file core_armv8mml.h.

◆ CONTROL_SPSEL_Pos [4/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 298 of file core_cm0.h.

◆ CONTROL_SPSEL_Pos [5/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 309 of file core_cm0plus.h.

◆ CONTROL_SPSEL_Pos [6/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 298 of file core_cm1.h.

◆ CONTROL_SPSEL_Pos [7/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 332 of file core_cm23.h.

◆ CONTROL_SPSEL_Pos [8/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 321 of file core_cm3.h.

◆ CONTROL_SPSEL_Pos [9/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 442 of file core_cm33.h.

◆ CONTROL_SPSEL_Pos [10/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 442 of file core_cm35p.h.

◆ CONTROL_SPSEL_Pos [11/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 387 of file core_cm4.h.

◆ CONTROL_SPSEL_Pos [12/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 402 of file core_cm7.h.

◆ CONTROL_SPSEL_Pos [13/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 304 of file core_sc000.h.

◆ CONTROL_SPSEL_Pos [14/14]

#define CONTROL_SPSEL_Pos 1U

CONTROL: SPSEL Position

Definition at line 321 of file core_sc300.h.

◆ CoreDebug [1/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

Definition at line 2050 of file core_armv81mml.h.

◆ CoreDebug [2/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

Definition at line 1127 of file core_armv8mbl.h.

◆ CoreDebug [3/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

Definition at line 1894 of file core_armv8mml.h.

◆ CoreDebug [4/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

Definition at line 1202 of file core_cm23.h.

◆ CoreDebug [5/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

Definition at line 1391 of file core_cm3.h.

◆ CoreDebug [6/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

Definition at line 1969 of file core_cm33.h.

◆ CoreDebug [7/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )

Core Debug configuration struct

Definition at line 1969 of file core_cm35p.h.

◆ CoreDebug [8/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

Definition at line 1561 of file core_cm4.h.

◆ CoreDebug [9/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

Definition at line 1784 of file core_cm7.h.

◆ CoreDebug [10/10]

#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

Core Debug configuration struct

Definition at line 1374 of file core_sc300.h.

◆ CoreDebug_BASE [1/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 2038 of file core_armv81mml.h.

◆ CoreDebug_BASE [2/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1116 of file core_armv8mbl.h.

◆ CoreDebug_BASE [3/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1882 of file core_armv8mml.h.

◆ CoreDebug_BASE [4/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1191 of file core_cm23.h.

◆ CoreDebug_BASE [5/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1379 of file core_cm3.h.

◆ CoreDebug_BASE [6/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1957 of file core_cm33.h.

◆ CoreDebug_BASE [7/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1957 of file core_cm35p.h.

◆ CoreDebug_BASE [8/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1549 of file core_cm4.h.

◆ CoreDebug_BASE [9/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1772 of file core_cm7.h.

◆ CoreDebug_BASE [10/10]

#define CoreDebug_BASE (0xE000EDF0UL)

Core Debug Base Address

Definition at line 1362 of file core_sc300.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [1/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1982 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [2/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1061 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [3/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1826 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [4/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1136 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [5/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1901 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Msk [6/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPIDEN Mask

Definition at line 1901 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [1/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1981 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [2/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1060 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [3/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1825 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [4/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1135 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [5/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1900 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPIDEN_Pos [6/6]

#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U

CoreDebug DAUTHCTRL: INTSPIDEN Position

Definition at line 1900 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [1/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1976 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [2/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1055 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [3/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1820 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [4/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1130 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [5/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1895 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk [6/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)

CoreDebug DAUTHCTRL: INTSPNIDEN, Mask

Definition at line 1895 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [1/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1975 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [2/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1054 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [3/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1819 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [4/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1129 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [5/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1894 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos [6/6]

#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U

CoreDebug DAUTHCTRL: INTSPNIDEN, Position

Definition at line 1894 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [1/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1985 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [2/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1064 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [3/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1829 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [4/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1139 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [5/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1904 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Msk [6/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)

CoreDebug DAUTHCTRL: SPIDENSEL Mask

Definition at line 1904 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [1/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1984 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [2/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1063 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [3/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1828 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [4/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1138 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [5/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1903 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPIDENSEL_Pos [6/6]

#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U

CoreDebug DAUTHCTRL: SPIDENSEL Position

Definition at line 1903 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [1/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1979 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [2/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1058 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [3/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1823 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [4/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1133 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [5/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1898 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk [6/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)

CoreDebug DAUTHCTRL: SPNIDENSEL Mask

Definition at line 1898 of file core_cm35p.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [1/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1978 of file core_armv81mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [2/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1057 of file core_armv8mbl.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [3/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1822 of file core_armv8mml.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [4/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1132 of file core_cm23.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [5/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1897 of file core_cm33.h.

◆ CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos [6/6]

#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U

CoreDebug DAUTHCTRL: SPNIDENSEL Position

Definition at line 1897 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [1/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1932 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [2/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1041 of file core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [3/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1776 of file core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [4/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1116 of file core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [5/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1296 of file core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [6/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1851 of file core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [7/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1851 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [8/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1466 of file core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [9/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1689 of file core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Msk [10/10]

#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)

CoreDebug DCRSR: REGSEL Mask

Definition at line 1279 of file core_sc300.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [1/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1931 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [2/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1040 of file core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [3/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1775 of file core_armv8mml.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [4/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1115 of file core_cm23.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [5/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1295 of file core_cm3.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [6/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1850 of file core_cm33.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [7/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1850 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [8/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1465 of file core_cm4.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [9/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1688 of file core_cm7.h.

◆ CoreDebug_DCRSR_REGSEL_Pos [10/10]

#define CoreDebug_DCRSR_REGSEL_Pos 0U

CoreDebug DCRSR: REGSEL Position

Definition at line 1278 of file core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [1/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1929 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [2/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1038 of file core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [3/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1773 of file core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [4/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1113 of file core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [5/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1293 of file core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [6/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1848 of file core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [7/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1848 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [8/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1463 of file core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [9/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1686 of file core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Msk [10/10]

#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)

CoreDebug DCRSR: REGWnR Mask

Definition at line 1276 of file core_sc300.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [1/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1928 of file core_armv81mml.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [2/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1037 of file core_armv8mbl.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [3/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1772 of file core_armv8mml.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [4/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1112 of file core_cm23.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [5/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1292 of file core_cm3.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [6/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1847 of file core_cm33.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [7/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1847 of file core_cm35p.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [8/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1462 of file core_cm4.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [9/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1685 of file core_cm7.h.

◆ CoreDebug_DCRSR_REGWnR_Pos [10/10]

#define CoreDebug_DCRSR_REGWnR_Pos 16U

CoreDebug DCRSR: REGWnR Position

Definition at line 1275 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [1/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1948 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [2/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1792 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [3/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1312 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [4/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1867 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [5/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1867 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [6/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1482 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [7/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1705 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Msk [8/8]

#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)

CoreDebug DEMCR: MON_EN Mask

Definition at line 1295 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [1/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1947 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [2/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1791 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [3/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1311 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [4/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1866 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [5/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1866 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [6/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1481 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [7/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1704 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_EN_Pos [8/8]

#define CoreDebug_DEMCR_MON_EN_Pos 16U

CoreDebug DEMCR: MON_EN Position

Definition at line 1294 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [1/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1945 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [2/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1789 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [3/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1309 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [4/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1864 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [5/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1864 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [6/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1479 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [7/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1702 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Msk [8/8]

#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)

CoreDebug DEMCR: MON_PEND Mask

Definition at line 1292 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [1/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1944 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [2/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1788 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [3/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1308 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [4/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1863 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [5/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1863 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [6/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1478 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [7/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1701 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_PEND_Pos [8/8]

#define CoreDebug_DEMCR_MON_PEND_Pos 17U

CoreDebug DEMCR: MON_PEND Position

Definition at line 1291 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [1/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1939 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [2/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1783 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [3/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1303 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [4/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1858 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [5/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1858 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [6/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1473 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [7/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1696 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Msk [8/8]

#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)

CoreDebug DEMCR: MON_REQ Mask

Definition at line 1286 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [1/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1938 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [2/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1782 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [3/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1302 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [4/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1857 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [5/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1857 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [6/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1472 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [7/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1695 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_REQ_Pos [8/8]

#define CoreDebug_DEMCR_MON_REQ_Pos 19U

CoreDebug DEMCR: MON_REQ Position

Definition at line 1285 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [1/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1942 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [2/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1786 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [3/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1306 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [4/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1861 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [5/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1861 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [6/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1476 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [7/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1699 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Msk [8/8]

#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)

CoreDebug DEMCR: MON_STEP Mask

Definition at line 1289 of file core_sc300.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [1/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1941 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [2/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1785 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [3/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1305 of file core_cm3.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [4/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1860 of file core_cm33.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [5/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1860 of file core_cm35p.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [6/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1475 of file core_cm4.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [7/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1698 of file core_cm7.h.

◆ CoreDebug_DEMCR_MON_STEP_Pos [8/8]

#define CoreDebug_DEMCR_MON_STEP_Pos 18U

CoreDebug DEMCR: MON_STEP Position

Definition at line 1288 of file core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [1/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1936 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [2/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1780 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [3/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1300 of file core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [4/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1855 of file core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [5/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1855 of file core_cm35p.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [6/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1470 of file core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [7/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1693 of file core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Msk [8/8]

#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)

CoreDebug DEMCR: TRCENA Mask

Definition at line 1283 of file core_sc300.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [1/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1935 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [2/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1779 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [3/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1299 of file core_cm3.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [4/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1854 of file core_cm33.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [5/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1854 of file core_cm35p.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [6/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1469 of file core_cm4.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [7/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1692 of file core_cm7.h.

◆ CoreDebug_DEMCR_TRCENA_Pos [8/8]

#define CoreDebug_DEMCR_TRCENA_Pos 24U

CoreDebug DEMCR: TRCENA Position

Definition at line 1282 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [1/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1957 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [2/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1801 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [3/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1321 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [4/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1876 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [5/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1876 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [6/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1491 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [7/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1714 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Msk [8/8]

#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)

CoreDebug DEMCR: VC_BUSERR Mask

Definition at line 1304 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [1/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1956 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [2/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1800 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [3/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1320 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [4/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1875 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [5/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1875 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [6/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1490 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [7/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1713 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_BUSERR_Pos [8/8]

#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U

CoreDebug DEMCR: VC_BUSERR Position

Definition at line 1303 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [1/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1963 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [2/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1807 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [3/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1327 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [4/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1882 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [5/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1882 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [6/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1497 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [7/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1720 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Msk [8/8]

#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)

CoreDebug DEMCR: VC_CHKERR Mask

Definition at line 1310 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [1/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1962 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [2/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1806 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [3/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1326 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [4/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1881 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [5/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1881 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [6/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1496 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [7/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1719 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_CHKERR_Pos [8/8]

#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U

CoreDebug DEMCR: VC_CHKERR Position

Definition at line 1309 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [1/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1972 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [2/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1051 of file core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [3/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1816 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [4/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1126 of file core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [5/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1336 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [6/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1891 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [7/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1891 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [8/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1506 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [9/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1729 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Msk [10/10]

#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)

CoreDebug DEMCR: VC_CORERESET Mask

Definition at line 1319 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [1/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1971 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [2/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1050 of file core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [3/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1815 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [4/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1125 of file core_cm23.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [5/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1335 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [6/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1890 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [7/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1890 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [8/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1505 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [9/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1728 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_CORERESET_Pos [10/10]

#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U

CoreDebug DEMCR: VC_CORERESET Position

Definition at line 1318 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [1/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1951 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [2/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1048 of file core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [3/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1795 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [4/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1123 of file core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [5/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1315 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [6/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1870 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [7/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1870 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [8/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1485 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [9/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1708 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Msk [10/10]

#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)

CoreDebug DEMCR: VC_HARDERR Mask

Definition at line 1298 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [1/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1950 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [2/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1047 of file core_armv8mbl.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [3/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1794 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [4/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1122 of file core_cm23.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [5/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1314 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [6/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1869 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [7/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1869 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [8/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1484 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [9/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1707 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_HARDERR_Pos [10/10]

#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U

CoreDebug DEMCR: VC_HARDERR Position

Definition at line 1297 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [1/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1954 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [2/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1798 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [3/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1318 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [4/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1873 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [5/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1873 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [6/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1488 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [7/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1711 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Msk [8/8]

#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)

CoreDebug DEMCR: VC_INTERR Mask

Definition at line 1301 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [1/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1953 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [2/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1797 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [3/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1317 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [4/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1872 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [5/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1872 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [6/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1487 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [7/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1710 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_INTERR_Pos [8/8]

#define CoreDebug_DEMCR_VC_INTERR_Pos 9U

CoreDebug DEMCR: VC_INTERR Position

Definition at line 1300 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [1/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1969 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [2/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1813 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [3/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1333 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [4/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1888 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [5/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1888 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [6/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1503 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [7/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1726 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Msk [8/8]

#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)

CoreDebug DEMCR: VC_MMERR Mask

Definition at line 1316 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [1/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1968 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [2/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1812 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [3/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1332 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [4/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1887 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [5/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1887 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [6/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1502 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [7/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1725 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_MMERR_Pos [8/8]

#define CoreDebug_DEMCR_VC_MMERR_Pos 4U

CoreDebug DEMCR: VC_MMERR Position

Definition at line 1315 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [1/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1966 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [2/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1810 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [3/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1330 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [4/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1885 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [5/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1885 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [6/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1500 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [7/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1723 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Msk [8/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)

CoreDebug DEMCR: VC_NOCPERR Mask

Definition at line 1313 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [1/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1965 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [2/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1809 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [3/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1329 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [4/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1884 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [5/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1884 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [6/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1499 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [7/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1722 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_NOCPERR_Pos [8/8]

#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U

CoreDebug DEMCR: VC_NOCPERR Position

Definition at line 1312 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [1/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1960 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [2/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1804 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [3/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1324 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [4/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1879 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [5/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1879 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [6/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1494 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [7/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1717 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Msk [8/8]

#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)

CoreDebug DEMCR: VC_STATERR Mask

Definition at line 1307 of file core_sc300.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [1/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1959 of file core_armv81mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [2/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1803 of file core_armv8mml.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [3/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1323 of file core_cm3.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [4/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1878 of file core_cm33.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [5/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1878 of file core_cm35p.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [6/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1493 of file core_cm4.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [7/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1716 of file core_cm7.h.

◆ CoreDebug_DEMCR_VC_STATERR_Pos [8/8]

#define CoreDebug_DEMCR_VC_STATERR_Pos 7U

CoreDebug DEMCR: VC_STATERR Position

Definition at line 1306 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [1/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1925 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [2/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1034 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [3/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1769 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [4/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1109 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [5/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1289 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [6/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1844 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [7/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1844 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [8/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1459 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [9/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1682 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Msk [10/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)

CoreDebug DHCSR: C_DEBUGEN Mask

Definition at line 1272 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [1/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1924 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [2/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1033 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [3/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1768 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [4/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1108 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [5/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1288 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [6/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1843 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [7/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1843 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [8/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1458 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [9/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1681 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_DEBUGEN_Pos [10/10]

#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U

CoreDebug DHCSR: C_DEBUGEN Position

Definition at line 1271 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [1/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1922 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [2/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1031 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [3/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1766 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [4/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1106 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [5/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1286 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [6/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1841 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [7/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1841 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [8/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1456 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [9/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1679 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Msk [10/10]

#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)

CoreDebug DHCSR: C_HALT Mask

Definition at line 1269 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [1/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1921 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [2/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1030 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [3/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1765 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [4/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1105 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [5/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1285 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [6/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1840 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [7/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1840 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [8/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1455 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [9/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1678 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_HALT_Pos [10/10]

#define CoreDebug_DHCSR_C_HALT_Pos 1U

CoreDebug DHCSR: C_HALT Position

Definition at line 1268 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [1/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1916 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [2/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1025 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [3/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1760 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [4/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1100 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [5/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1280 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [6/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1835 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [7/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1835 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [8/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1450 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [9/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1673 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Msk [10/10]

#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)

CoreDebug DHCSR: C_MASKINTS Mask

Definition at line 1263 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [1/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1915 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [2/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1024 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [3/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1759 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [4/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1099 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [5/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1279 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [6/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1834 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [7/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1834 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [8/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1449 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [9/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1672 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_MASKINTS_Pos [10/10]

#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U

CoreDebug DHCSR: C_MASKINTS Position

Definition at line 1262 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [1/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1913 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [2/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1757 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [3/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1277 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [4/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1832 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [5/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1832 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [6/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1447 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [7/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1670 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Msk [8/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

CoreDebug DHCSR: C_SNAPSTALL Mask

Definition at line 1260 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [1/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1912 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [2/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1756 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [3/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1276 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [4/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1831 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [5/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1831 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [6/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1446 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [7/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1669 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_SNAPSTALL_Pos [8/8]

#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U

CoreDebug DHCSR: C_SNAPSTALL Position

Definition at line 1259 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [1/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1919 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [2/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1028 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [3/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1763 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [4/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1103 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [5/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1283 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [6/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1838 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [7/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1838 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [8/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1453 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [9/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1676 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Msk [10/10]

#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)

CoreDebug DHCSR: C_STEP Mask

Definition at line 1266 of file core_sc300.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [1/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1918 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [2/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1027 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [3/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1762 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [4/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1102 of file core_cm23.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [5/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1282 of file core_cm3.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [6/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1837 of file core_cm33.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [7/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1837 of file core_cm35p.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [8/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1452 of file core_cm4.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [9/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1675 of file core_cm7.h.

◆ CoreDebug_DHCSR_C_STEP_Pos [10/10]

#define CoreDebug_DHCSR_C_STEP_Pos 2U

CoreDebug DHCSR: C_STEP Position

Definition at line 1265 of file core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [1/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1889 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [2/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1001 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [3/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1733 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [4/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1076 of file core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [5/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1256 of file core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [6/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1808 of file core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [7/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1808 of file core_cm35p.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [8/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1426 of file core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [9/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1649 of file core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Msk [10/10]

#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)

CoreDebug DHCSR: DBGKEY Mask

Definition at line 1239 of file core_sc300.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [1/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1888 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [2/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1000 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [3/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1732 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [4/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1075 of file core_cm23.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [5/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1255 of file core_cm3.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [6/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1807 of file core_cm33.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [7/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1807 of file core_cm35p.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [8/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1425 of file core_cm4.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [9/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1648 of file core_cm7.h.

◆ CoreDebug_DHCSR_DBGKEY_Pos [10/10]

#define CoreDebug_DHCSR_DBGKEY_Pos 16U

CoreDebug DHCSR: DBGKEY Position

Definition at line 1238 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [1/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1907 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [2/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1019 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [3/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1751 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [4/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1094 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [5/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1271 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [6/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1826 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [7/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1826 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [8/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1441 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [9/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1664 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Msk [10/10]

#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)

CoreDebug DHCSR: S_HALT Mask

Definition at line 1254 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [1/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1906 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [2/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1018 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [3/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1750 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [4/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1093 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [5/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1270 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [6/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1825 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [7/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1825 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [8/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1440 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [9/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1663 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_HALT_Pos [10/10]

#define CoreDebug_DHCSR_S_HALT_Pos 17U

CoreDebug DHCSR: S_HALT Position

Definition at line 1253 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [1/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1901 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [2/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1013 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [3/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1745 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [4/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1088 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [5/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1265 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [6/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1820 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [7/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1820 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [8/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1435 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [9/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1658 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Msk [10/10]

#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)

CoreDebug DHCSR: S_LOCKUP Mask

Definition at line 1248 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [1/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1900 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [2/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1012 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [3/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1744 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [4/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1087 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [5/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1264 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [6/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1819 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [7/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1819 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [8/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1434 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [9/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1657 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_LOCKUP_Pos [10/10]

#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U

CoreDebug DHCSR: S_LOCKUP Position

Definition at line 1247 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [1/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1910 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [2/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1022 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [3/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1754 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [4/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1097 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [5/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1274 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [6/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1829 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [7/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1829 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [8/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1444 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [9/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1667 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Msk [10/10]

#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)

CoreDebug DHCSR: S_REGRDY Mask

Definition at line 1257 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [1/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1909 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [2/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1021 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [3/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1753 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [4/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1096 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [5/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1273 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [6/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1828 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [7/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1828 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [8/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1443 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [9/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1666 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_REGRDY_Pos [10/10]

#define CoreDebug_DHCSR_S_REGRDY_Pos 16U

CoreDebug DHCSR: S_REGRDY Position

Definition at line 1256 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [1/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1895 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [2/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1007 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [3/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1739 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [4/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1082 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [5/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1259 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [6/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1814 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [7/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1814 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [8/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1429 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [9/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1652 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Msk [10/10]

#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)

CoreDebug DHCSR: S_RESET_ST Mask

Definition at line 1242 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [1/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1894 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [2/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1006 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [3/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1738 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [4/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1081 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [5/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1258 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [6/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1813 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [7/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1813 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [8/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1428 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [9/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1651 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_RESET_ST_Pos [10/10]

#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U

CoreDebug DHCSR: S_RESET_ST Position

Definition at line 1241 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [1/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1892 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [2/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1004 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [3/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1736 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [4/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1079 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [5/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1811 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Msk [6/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)

CoreDebug DHCSR: S_RESTART_ST Mask

Definition at line 1811 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [1/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1891 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [2/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1003 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [3/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1735 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [4/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1078 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [5/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1810 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RESTART_ST_Pos [6/6]

#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U

CoreDebug DHCSR: S_RESTART_ST Position

Definition at line 1810 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [1/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1898 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [2/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1010 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [3/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1742 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [4/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1085 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [5/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1262 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [6/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1817 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [7/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1817 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [8/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1432 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [9/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1655 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Msk [10/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

CoreDebug DHCSR: S_RETIRE_ST Mask

Definition at line 1245 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [1/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1897 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [2/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1009 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [3/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1741 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [4/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1084 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [5/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1261 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [6/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1816 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [7/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1816 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [8/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1431 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [9/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1654 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_RETIRE_ST_Pos [10/10]

#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U

CoreDebug DHCSR: S_RETIRE_ST Position

Definition at line 1244 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [1/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1904 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [2/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1016 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [3/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1748 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [4/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1091 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [5/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1268 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [6/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1823 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [7/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1823 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [8/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1438 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [9/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1661 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_SLEEP_Msk [10/10]

#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)

CoreDebug DHCSR: S_SLEEP Mask

Definition at line 1251 of file core_sc300.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [1/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1903 of file core_armv81mml.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [2/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1015 of file core_armv8mbl.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [3/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1747 of file core_armv8mml.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [4/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1090 of file core_cm23.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [5/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1267 of file core_cm3.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [6/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1822 of file core_cm33.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [7/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1822 of file core_cm35p.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [8/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1437 of file core_cm4.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [9/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1660 of file core_cm7.h.

◆ CoreDebug_DHCSR_S_SLEEP_Pos [10/10]

#define CoreDebug_DHCSR_S_SLEEP_Pos 18U

CoreDebug DHCSR: S_SLEEP Position

Definition at line 1250 of file core_sc300.h.

◆ CoreDebug_DSCSR_CDS_Msk [1/6]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

CoreDebug DSCSR: CDS Mask

Definition at line 1989 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_CDS_Msk [2/6]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

CoreDebug DSCSR: CDS Mask

Definition at line 1068 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_CDS_Msk [3/6]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

CoreDebug DSCSR: CDS Mask

Definition at line 1833 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_CDS_Msk [4/6]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

CoreDebug DSCSR: CDS Mask

Definition at line 1143 of file core_cm23.h.

◆ CoreDebug_DSCSR_CDS_Msk [5/6]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

CoreDebug DSCSR: CDS Mask

Definition at line 1908 of file core_cm33.h.

◆ CoreDebug_DSCSR_CDS_Msk [6/6]

#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)

CoreDebug DSCSR: CDS Mask

Definition at line 1908 of file core_cm35p.h.

◆ CoreDebug_DSCSR_CDS_Pos [1/6]

#define CoreDebug_DSCSR_CDS_Pos 16U

CoreDebug DSCSR: CDS Position

Definition at line 1988 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_CDS_Pos [2/6]

#define CoreDebug_DSCSR_CDS_Pos 16U

CoreDebug DSCSR: CDS Position

Definition at line 1067 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_CDS_Pos [3/6]

#define CoreDebug_DSCSR_CDS_Pos 16U

CoreDebug DSCSR: CDS Position

Definition at line 1832 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_CDS_Pos [4/6]

#define CoreDebug_DSCSR_CDS_Pos 16U

CoreDebug DSCSR: CDS Position

Definition at line 1142 of file core_cm23.h.

◆ CoreDebug_DSCSR_CDS_Pos [5/6]

#define CoreDebug_DSCSR_CDS_Pos 16U

CoreDebug DSCSR: CDS Position

Definition at line 1907 of file core_cm33.h.

◆ CoreDebug_DSCSR_CDS_Pos [6/6]

#define CoreDebug_DSCSR_CDS_Pos 16U

CoreDebug DSCSR: CDS Position

Definition at line 1907 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [1/6]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

CoreDebug DSCSR: SBRSEL Mask

Definition at line 1992 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [2/6]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

CoreDebug DSCSR: SBRSEL Mask

Definition at line 1071 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [3/6]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

CoreDebug DSCSR: SBRSEL Mask

Definition at line 1836 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [4/6]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

CoreDebug DSCSR: SBRSEL Mask

Definition at line 1146 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [5/6]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

CoreDebug DSCSR: SBRSEL Mask

Definition at line 1911 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSEL_Msk [6/6]

#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)

CoreDebug DSCSR: SBRSEL Mask

Definition at line 1911 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [1/6]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

CoreDebug DSCSR: SBRSEL Position

Definition at line 1991 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [2/6]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

CoreDebug DSCSR: SBRSEL Position

Definition at line 1070 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [3/6]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

CoreDebug DSCSR: SBRSEL Position

Definition at line 1835 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [4/6]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

CoreDebug DSCSR: SBRSEL Position

Definition at line 1145 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [5/6]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

CoreDebug DSCSR: SBRSEL Position

Definition at line 1910 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSEL_Pos [6/6]

#define CoreDebug_DSCSR_SBRSEL_Pos 1U

CoreDebug DSCSR: SBRSEL Position

Definition at line 1910 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [1/6]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1995 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [2/6]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1074 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [3/6]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1839 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [4/6]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1149 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [5/6]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1914 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSELEN_Msk [6/6]

#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)

CoreDebug DSCSR: SBRSELEN Mask

Definition at line 1914 of file core_cm35p.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [1/6]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

CoreDebug DSCSR: SBRSELEN Position

Definition at line 1994 of file core_armv81mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [2/6]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

CoreDebug DSCSR: SBRSELEN Position

Definition at line 1073 of file core_armv8mbl.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [3/6]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

CoreDebug DSCSR: SBRSELEN Position

Definition at line 1838 of file core_armv8mml.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [4/6]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

CoreDebug DSCSR: SBRSELEN Position

Definition at line 1148 of file core_cm23.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [5/6]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

CoreDebug DSCSR: SBRSELEN Position

Definition at line 1913 of file core_cm33.h.

◆ CoreDebug_DSCSR_SBRSELEN_Pos [6/6]

#define CoreDebug_DSCSR_SBRSELEN_Pos 0U

CoreDebug DSCSR: SBRSELEN Position

Definition at line 1913 of file core_cm35p.h.

◆ DWT [1/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 2048 of file core_armv81mml.h.

◆ DWT [2/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1125 of file core_armv8mbl.h.

◆ DWT [3/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1892 of file core_armv8mml.h.

◆ DWT [4/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1200 of file core_cm23.h.

◆ DWT [5/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1389 of file core_cm3.h.

◆ DWT [6/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1967 of file core_cm33.h.

◆ DWT [7/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1967 of file core_cm35p.h.

◆ DWT [8/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1559 of file core_cm4.h.

◆ DWT [9/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1782 of file core_cm7.h.

◆ DWT [10/10]

#define DWT ((DWT_Type *) DWT_BASE )

DWT configuration struct

Definition at line 1372 of file core_sc300.h.

◆ DWT_BASE [1/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 2036 of file core_armv81mml.h.

◆ DWT_BASE [2/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1114 of file core_armv8mbl.h.

◆ DWT_BASE [3/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1880 of file core_armv8mml.h.

◆ DWT_BASE [4/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1189 of file core_cm23.h.

◆ DWT_BASE [5/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1377 of file core_cm3.h.

◆ DWT_BASE [6/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1955 of file core_cm33.h.

◆ DWT_BASE [7/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1955 of file core_cm35p.h.

◆ DWT_BASE [8/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1547 of file core_cm4.h.

◆ DWT_BASE [9/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1770 of file core_cm7.h.

◆ DWT_BASE [10/10]

#define DWT_BASE (0xE0001000UL)

DWT Base Address

Definition at line 1360 of file core_sc300.h.

◆ DWT_CPICNT_CPICNT_Msk [1/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 1341 of file core_armv81mml.h.

◆ DWT_CPICNT_CPICNT_Msk [2/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 1245 of file core_armv8mml.h.

◆ DWT_CPICNT_CPICNT_Msk [3/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 925 of file core_cm3.h.

◆ DWT_CPICNT_CPICNT_Msk [4/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 1245 of file core_cm33.h.

◆ DWT_CPICNT_CPICNT_Msk [5/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 1245 of file core_cm35p.h.

◆ DWT_CPICNT_CPICNT_Msk [6/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 983 of file core_cm4.h.

◆ DWT_CPICNT_CPICNT_Msk [7/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 1206 of file core_cm7.h.

◆ DWT_CPICNT_CPICNT_Msk [8/8]

#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)

DWT CPICNT: CPICNT Mask

Definition at line 910 of file core_sc300.h.

◆ DWT_CPICNT_CPICNT_Pos [1/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 1340 of file core_armv81mml.h.

◆ DWT_CPICNT_CPICNT_Pos [2/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 1244 of file core_armv8mml.h.

◆ DWT_CPICNT_CPICNT_Pos [3/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 924 of file core_cm3.h.

◆ DWT_CPICNT_CPICNT_Pos [4/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 1244 of file core_cm33.h.

◆ DWT_CPICNT_CPICNT_Pos [5/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 1244 of file core_cm35p.h.

◆ DWT_CPICNT_CPICNT_Pos [6/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 982 of file core_cm4.h.

◆ DWT_CPICNT_CPICNT_Pos [7/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 1205 of file core_cm7.h.

◆ DWT_CPICNT_CPICNT_Pos [8/8]

#define DWT_CPICNT_CPICNT_Pos 0U

DWT CPICNT: CPICNT Position

Definition at line 909 of file core_sc300.h.

◆ DWT_CTRL_CPIEVTENA_Msk [1/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 1316 of file core_armv81mml.h.

◆ DWT_CTRL_CPIEVTENA_Msk [2/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 1220 of file core_armv8mml.h.

◆ DWT_CTRL_CPIEVTENA_Msk [3/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 900 of file core_cm3.h.

◆ DWT_CTRL_CPIEVTENA_Msk [4/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 1220 of file core_cm33.h.

◆ DWT_CTRL_CPIEVTENA_Msk [5/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 1220 of file core_cm35p.h.

◆ DWT_CTRL_CPIEVTENA_Msk [6/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 958 of file core_cm4.h.

◆ DWT_CTRL_CPIEVTENA_Msk [7/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 1181 of file core_cm7.h.

◆ DWT_CTRL_CPIEVTENA_Msk [8/8]

#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)

DWT CTRL: CPIEVTENA Mask

Definition at line 885 of file core_sc300.h.

◆ DWT_CTRL_CPIEVTENA_Pos [1/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 1315 of file core_armv81mml.h.

◆ DWT_CTRL_CPIEVTENA_Pos [2/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 1219 of file core_armv8mml.h.

◆ DWT_CTRL_CPIEVTENA_Pos [3/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 899 of file core_cm3.h.

◆ DWT_CTRL_CPIEVTENA_Pos [4/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 1219 of file core_cm33.h.

◆ DWT_CTRL_CPIEVTENA_Pos [5/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 1219 of file core_cm35p.h.

◆ DWT_CTRL_CPIEVTENA_Pos [6/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 957 of file core_cm4.h.

◆ DWT_CTRL_CPIEVTENA_Pos [7/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 1180 of file core_cm7.h.

◆ DWT_CTRL_CPIEVTENA_Pos [8/8]

#define DWT_CTRL_CPIEVTENA_Pos 17U

DWT CTRL: CPIEVTENA Position

Definition at line 884 of file core_sc300.h.

◆ DWT_CTRL_CYCCNTENA_Msk [1/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 1337 of file core_armv81mml.h.

◆ DWT_CTRL_CYCCNTENA_Msk [2/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 1241 of file core_armv8mml.h.

◆ DWT_CTRL_CYCCNTENA_Msk [3/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 921 of file core_cm3.h.

◆ DWT_CTRL_CYCCNTENA_Msk [4/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 1241 of file core_cm33.h.

◆ DWT_CTRL_CYCCNTENA_Msk [5/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 1241 of file core_cm35p.h.

◆ DWT_CTRL_CYCCNTENA_Msk [6/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 979 of file core_cm4.h.

◆ DWT_CTRL_CYCCNTENA_Msk [7/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 1202 of file core_cm7.h.

◆ DWT_CTRL_CYCCNTENA_Msk [8/8]

#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)

DWT CTRL: CYCCNTENA Mask

Definition at line 906 of file core_sc300.h.

◆ DWT_CTRL_CYCCNTENA_Pos [1/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 1336 of file core_armv81mml.h.

◆ DWT_CTRL_CYCCNTENA_Pos [2/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 1240 of file core_armv8mml.h.

◆ DWT_CTRL_CYCCNTENA_Pos [3/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 920 of file core_cm3.h.

◆ DWT_CTRL_CYCCNTENA_Pos [4/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 1240 of file core_cm33.h.

◆ DWT_CTRL_CYCCNTENA_Pos [5/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 1240 of file core_cm35p.h.

◆ DWT_CTRL_CYCCNTENA_Pos [6/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 978 of file core_cm4.h.

◆ DWT_CTRL_CYCCNTENA_Pos [7/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 1201 of file core_cm7.h.

◆ DWT_CTRL_CYCCNTENA_Pos [8/8]

#define DWT_CTRL_CYCCNTENA_Pos 0U

DWT CTRL: CYCCNTENA Position

Definition at line 905 of file core_sc300.h.

◆ DWT_CTRL_CYCDISS_Msk [1/4]

#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

DWT CTRL: CYCDISS Mask

Definition at line 1298 of file core_armv81mml.h.

◆ DWT_CTRL_CYCDISS_Msk [2/4]

#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

DWT CTRL: CYCDISS Mask

Definition at line 1202 of file core_armv8mml.h.

◆ DWT_CTRL_CYCDISS_Msk [3/4]

#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

DWT CTRL: CYCDISS Mask

Definition at line 1202 of file core_cm33.h.

◆ DWT_CTRL_CYCDISS_Msk [4/4]

#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)

DWT CTRL: CYCDISS Mask

Definition at line 1202 of file core_cm35p.h.

◆ DWT_CTRL_CYCDISS_Pos [1/4]

#define DWT_CTRL_CYCDISS_Pos 23U

DWT CTRL: CYCDISS Position

Definition at line 1297 of file core_armv81mml.h.

◆ DWT_CTRL_CYCDISS_Pos [2/4]

#define DWT_CTRL_CYCDISS_Pos 23U

DWT CTRL: CYCDISS Position

Definition at line 1201 of file core_armv8mml.h.

◆ DWT_CTRL_CYCDISS_Pos [3/4]

#define DWT_CTRL_CYCDISS_Pos 23U

DWT CTRL: CYCDISS Position

Definition at line 1201 of file core_cm33.h.

◆ DWT_CTRL_CYCDISS_Pos [4/4]

#define DWT_CTRL_CYCDISS_Pos 23U

DWT CTRL: CYCDISS Position

Definition at line 1201 of file core_cm35p.h.

◆ DWT_CTRL_CYCEVTENA_Msk [1/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 1301 of file core_armv81mml.h.

◆ DWT_CTRL_CYCEVTENA_Msk [2/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 1205 of file core_armv8mml.h.

◆ DWT_CTRL_CYCEVTENA_Msk [3/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 885 of file core_cm3.h.

◆ DWT_CTRL_CYCEVTENA_Msk [4/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 1205 of file core_cm33.h.

◆ DWT_CTRL_CYCEVTENA_Msk [5/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 1205 of file core_cm35p.h.

◆ DWT_CTRL_CYCEVTENA_Msk [6/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 943 of file core_cm4.h.

◆ DWT_CTRL_CYCEVTENA_Msk [7/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 1166 of file core_cm7.h.

◆ DWT_CTRL_CYCEVTENA_Msk [8/8]

#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)

DWT CTRL: CYCEVTENA Mask

Definition at line 870 of file core_sc300.h.

◆ DWT_CTRL_CYCEVTENA_Pos [1/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 1300 of file core_armv81mml.h.

◆ DWT_CTRL_CYCEVTENA_Pos [2/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 1204 of file core_armv8mml.h.

◆ DWT_CTRL_CYCEVTENA_Pos [3/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 884 of file core_cm3.h.

◆ DWT_CTRL_CYCEVTENA_Pos [4/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 1204 of file core_cm33.h.

◆ DWT_CTRL_CYCEVTENA_Pos [5/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 1204 of file core_cm35p.h.

◆ DWT_CTRL_CYCEVTENA_Pos [6/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 942 of file core_cm4.h.

◆ DWT_CTRL_CYCEVTENA_Pos [7/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 1165 of file core_cm7.h.

◆ DWT_CTRL_CYCEVTENA_Pos [8/8]

#define DWT_CTRL_CYCEVTENA_Pos 22U

DWT CTRL: CYCEVTENA Position

Definition at line 869 of file core_sc300.h.

◆ DWT_CTRL_CYCTAP_Msk [1/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 1328 of file core_armv81mml.h.

◆ DWT_CTRL_CYCTAP_Msk [2/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 1232 of file core_armv8mml.h.

◆ DWT_CTRL_CYCTAP_Msk [3/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 912 of file core_cm3.h.

◆ DWT_CTRL_CYCTAP_Msk [4/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 1232 of file core_cm33.h.

◆ DWT_CTRL_CYCTAP_Msk [5/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 1232 of file core_cm35p.h.

◆ DWT_CTRL_CYCTAP_Msk [6/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 970 of file core_cm4.h.

◆ DWT_CTRL_CYCTAP_Msk [7/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 1193 of file core_cm7.h.

◆ DWT_CTRL_CYCTAP_Msk [8/8]

#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)

DWT CTRL: CYCTAP Mask

Definition at line 897 of file core_sc300.h.

◆ DWT_CTRL_CYCTAP_Pos [1/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 1327 of file core_armv81mml.h.

◆ DWT_CTRL_CYCTAP_Pos [2/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 1231 of file core_armv8mml.h.

◆ DWT_CTRL_CYCTAP_Pos [3/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 911 of file core_cm3.h.

◆ DWT_CTRL_CYCTAP_Pos [4/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 1231 of file core_cm33.h.

◆ DWT_CTRL_CYCTAP_Pos [5/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 1231 of file core_cm35p.h.

◆ DWT_CTRL_CYCTAP_Pos [6/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 969 of file core_cm4.h.

◆ DWT_CTRL_CYCTAP_Pos [7/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 1192 of file core_cm7.h.

◆ DWT_CTRL_CYCTAP_Pos [8/8]

#define DWT_CTRL_CYCTAP_Pos 9U

DWT CTRL: CYCTAP Position

Definition at line 896 of file core_sc300.h.

◆ DWT_CTRL_EXCEVTENA_Msk [1/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 1313 of file core_armv81mml.h.

◆ DWT_CTRL_EXCEVTENA_Msk [2/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 1217 of file core_armv8mml.h.

◆ DWT_CTRL_EXCEVTENA_Msk [3/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 897 of file core_cm3.h.

◆ DWT_CTRL_EXCEVTENA_Msk [4/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 1217 of file core_cm33.h.

◆ DWT_CTRL_EXCEVTENA_Msk [5/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 1217 of file core_cm35p.h.

◆ DWT_CTRL_EXCEVTENA_Msk [6/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 955 of file core_cm4.h.

◆ DWT_CTRL_EXCEVTENA_Msk [7/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 1178 of file core_cm7.h.

◆ DWT_CTRL_EXCEVTENA_Msk [8/8]

#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)

DWT CTRL: EXCEVTENA Mask

Definition at line 882 of file core_sc300.h.

◆ DWT_CTRL_EXCEVTENA_Pos [1/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 1312 of file core_armv81mml.h.

◆ DWT_CTRL_EXCEVTENA_Pos [2/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 1216 of file core_armv8mml.h.

◆ DWT_CTRL_EXCEVTENA_Pos [3/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 896 of file core_cm3.h.

◆ DWT_CTRL_EXCEVTENA_Pos [4/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 1216 of file core_cm33.h.

◆ DWT_CTRL_EXCEVTENA_Pos [5/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 1216 of file core_cm35p.h.

◆ DWT_CTRL_EXCEVTENA_Pos [6/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 954 of file core_cm4.h.

◆ DWT_CTRL_EXCEVTENA_Pos [7/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 1177 of file core_cm7.h.

◆ DWT_CTRL_EXCEVTENA_Pos [8/8]

#define DWT_CTRL_EXCEVTENA_Pos 18U

DWT CTRL: EXCEVTENA Position

Definition at line 881 of file core_sc300.h.

◆ DWT_CTRL_EXCTRCENA_Msk [1/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 1319 of file core_armv81mml.h.

◆ DWT_CTRL_EXCTRCENA_Msk [2/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 1223 of file core_armv8mml.h.

◆ DWT_CTRL_EXCTRCENA_Msk [3/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 903 of file core_cm3.h.

◆ DWT_CTRL_EXCTRCENA_Msk [4/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 1223 of file core_cm33.h.

◆ DWT_CTRL_EXCTRCENA_Msk [5/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 1223 of file core_cm35p.h.

◆ DWT_CTRL_EXCTRCENA_Msk [6/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 961 of file core_cm4.h.

◆ DWT_CTRL_EXCTRCENA_Msk [7/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 1184 of file core_cm7.h.

◆ DWT_CTRL_EXCTRCENA_Msk [8/8]

#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)

DWT CTRL: EXCTRCENA Mask

Definition at line 888 of file core_sc300.h.

◆ DWT_CTRL_EXCTRCENA_Pos [1/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 1318 of file core_armv81mml.h.

◆ DWT_CTRL_EXCTRCENA_Pos [2/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 1222 of file core_armv8mml.h.

◆ DWT_CTRL_EXCTRCENA_Pos [3/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 902 of file core_cm3.h.

◆ DWT_CTRL_EXCTRCENA_Pos [4/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 1222 of file core_cm33.h.

◆ DWT_CTRL_EXCTRCENA_Pos [5/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 1222 of file core_cm35p.h.

◆ DWT_CTRL_EXCTRCENA_Pos [6/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 960 of file core_cm4.h.

◆ DWT_CTRL_EXCTRCENA_Pos [7/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 1183 of file core_cm7.h.

◆ DWT_CTRL_EXCTRCENA_Pos [8/8]

#define DWT_CTRL_EXCTRCENA_Pos 16U

DWT CTRL: EXCTRCENA Position

Definition at line 887 of file core_sc300.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [1/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 1304 of file core_armv81mml.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [2/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 1208 of file core_armv8mml.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [3/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 888 of file core_cm3.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [4/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 1208 of file core_cm33.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [5/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 1208 of file core_cm35p.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [6/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 946 of file core_cm4.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [7/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 1169 of file core_cm7.h.

◆ DWT_CTRL_FOLDEVTENA_Msk [8/8]

#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)

DWT CTRL: FOLDEVTENA Mask

Definition at line 873 of file core_sc300.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [1/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 1303 of file core_armv81mml.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [2/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 1207 of file core_armv8mml.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [3/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 887 of file core_cm3.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [4/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 1207 of file core_cm33.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [5/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 1207 of file core_cm35p.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [6/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 945 of file core_cm4.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [7/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 1168 of file core_cm7.h.

◆ DWT_CTRL_FOLDEVTENA_Pos [8/8]

#define DWT_CTRL_FOLDEVTENA_Pos 21U

DWT CTRL: FOLDEVTENA Position

Definition at line 872 of file core_sc300.h.

◆ DWT_CTRL_LSUEVTENA_Msk [1/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 1307 of file core_armv81mml.h.

◆ DWT_CTRL_LSUEVTENA_Msk [2/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 1211 of file core_armv8mml.h.

◆ DWT_CTRL_LSUEVTENA_Msk [3/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 891 of file core_cm3.h.

◆ DWT_CTRL_LSUEVTENA_Msk [4/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 1211 of file core_cm33.h.

◆ DWT_CTRL_LSUEVTENA_Msk [5/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 1211 of file core_cm35p.h.

◆ DWT_CTRL_LSUEVTENA_Msk [6/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 949 of file core_cm4.h.

◆ DWT_CTRL_LSUEVTENA_Msk [7/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 1172 of file core_cm7.h.

◆ DWT_CTRL_LSUEVTENA_Msk [8/8]

#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)

DWT CTRL: LSUEVTENA Mask

Definition at line 876 of file core_sc300.h.

◆ DWT_CTRL_LSUEVTENA_Pos [1/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 1306 of file core_armv81mml.h.

◆ DWT_CTRL_LSUEVTENA_Pos [2/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 1210 of file core_armv8mml.h.

◆ DWT_CTRL_LSUEVTENA_Pos [3/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 890 of file core_cm3.h.

◆ DWT_CTRL_LSUEVTENA_Pos [4/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 1210 of file core_cm33.h.

◆ DWT_CTRL_LSUEVTENA_Pos [5/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 1210 of file core_cm35p.h.

◆ DWT_CTRL_LSUEVTENA_Pos [6/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 948 of file core_cm4.h.

◆ DWT_CTRL_LSUEVTENA_Pos [7/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 1171 of file core_cm7.h.

◆ DWT_CTRL_LSUEVTENA_Pos [8/8]

#define DWT_CTRL_LSUEVTENA_Pos 20U

DWT CTRL: LSUEVTENA Position

Definition at line 875 of file core_sc300.h.

◆ DWT_CTRL_NOCYCCNT_Msk [1/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 1292 of file core_armv81mml.h.

◆ DWT_CTRL_NOCYCCNT_Msk [2/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 691 of file core_armv8mbl.h.

◆ DWT_CTRL_NOCYCCNT_Msk [3/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 1196 of file core_armv8mml.h.

◆ DWT_CTRL_NOCYCCNT_Msk [4/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 691 of file core_cm23.h.

◆ DWT_CTRL_NOCYCCNT_Msk [5/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 879 of file core_cm3.h.

◆ DWT_CTRL_NOCYCCNT_Msk [6/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 1196 of file core_cm33.h.

◆ DWT_CTRL_NOCYCCNT_Msk [7/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 1196 of file core_cm35p.h.

◆ DWT_CTRL_NOCYCCNT_Msk [8/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 937 of file core_cm4.h.

◆ DWT_CTRL_NOCYCCNT_Msk [9/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 1160 of file core_cm7.h.

◆ DWT_CTRL_NOCYCCNT_Msk [10/10]

#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)

DWT CTRL: NOCYCCNT Mask

Definition at line 864 of file core_sc300.h.

◆ DWT_CTRL_NOCYCCNT_Pos [1/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 1291 of file core_armv81mml.h.

◆ DWT_CTRL_NOCYCCNT_Pos [2/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 690 of file core_armv8mbl.h.

◆ DWT_CTRL_NOCYCCNT_Pos [3/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 1195 of file core_armv8mml.h.

◆ DWT_CTRL_NOCYCCNT_Pos [4/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 690 of file core_cm23.h.

◆ DWT_CTRL_NOCYCCNT_Pos [5/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 878 of file core_cm3.h.

◆ DWT_CTRL_NOCYCCNT_Pos [6/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 1195 of file core_cm33.h.

◆ DWT_CTRL_NOCYCCNT_Pos [7/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 1195 of file core_cm35p.h.

◆ DWT_CTRL_NOCYCCNT_Pos [8/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 936 of file core_cm4.h.

◆ DWT_CTRL_NOCYCCNT_Pos [9/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 1159 of file core_cm7.h.

◆ DWT_CTRL_NOCYCCNT_Pos [10/10]

#define DWT_CTRL_NOCYCCNT_Pos 25U

DWT CTRL: NOCYCCNT Position

Definition at line 863 of file core_sc300.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [1/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 1289 of file core_armv81mml.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [2/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 688 of file core_armv8mbl.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [3/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 1193 of file core_armv8mml.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [4/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 688 of file core_cm23.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [5/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 876 of file core_cm3.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [6/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 1193 of file core_cm33.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [7/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 1193 of file core_cm35p.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [8/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 934 of file core_cm4.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [9/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 1157 of file core_cm7.h.

◆ DWT_CTRL_NOEXTTRIG_Msk [10/10]

#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)

DWT CTRL: NOEXTTRIG Mask

Definition at line 861 of file core_sc300.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [1/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 1288 of file core_armv81mml.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [2/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 687 of file core_armv8mbl.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [3/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 1192 of file core_armv8mml.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [4/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 687 of file core_cm23.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [5/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 875 of file core_cm3.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [6/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 1192 of file core_cm33.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [7/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 1192 of file core_cm35p.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [8/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 933 of file core_cm4.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [9/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 1156 of file core_cm7.h.

◆ DWT_CTRL_NOEXTTRIG_Pos [10/10]

#define DWT_CTRL_NOEXTTRIG_Pos 26U

DWT CTRL: NOEXTTRIG Position

Definition at line 860 of file core_sc300.h.

◆ DWT_CTRL_NOPRFCNT_Msk [1/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 1295 of file core_armv81mml.h.

◆ DWT_CTRL_NOPRFCNT_Msk [2/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 694 of file core_armv8mbl.h.

◆ DWT_CTRL_NOPRFCNT_Msk [3/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 1199 of file core_armv8mml.h.

◆ DWT_CTRL_NOPRFCNT_Msk [4/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 694 of file core_cm23.h.

◆ DWT_CTRL_NOPRFCNT_Msk [5/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 882 of file core_cm3.h.

◆ DWT_CTRL_NOPRFCNT_Msk [6/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 1199 of file core_cm33.h.

◆ DWT_CTRL_NOPRFCNT_Msk [7/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 1199 of file core_cm35p.h.

◆ DWT_CTRL_NOPRFCNT_Msk [8/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 940 of file core_cm4.h.

◆ DWT_CTRL_NOPRFCNT_Msk [9/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 1163 of file core_cm7.h.

◆ DWT_CTRL_NOPRFCNT_Msk [10/10]

#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)

DWT CTRL: NOPRFCNT Mask

Definition at line 867 of file core_sc300.h.

◆ DWT_CTRL_NOPRFCNT_Pos [1/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 1294 of file core_armv81mml.h.

◆ DWT_CTRL_NOPRFCNT_Pos [2/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 693 of file core_armv8mbl.h.

◆ DWT_CTRL_NOPRFCNT_Pos [3/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 1198 of file core_armv8mml.h.

◆ DWT_CTRL_NOPRFCNT_Pos [4/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 693 of file core_cm23.h.

◆ DWT_CTRL_NOPRFCNT_Pos [5/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 881 of file core_cm3.h.

◆ DWT_CTRL_NOPRFCNT_Pos [6/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 1198 of file core_cm33.h.

◆ DWT_CTRL_NOPRFCNT_Pos [7/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 1198 of file core_cm35p.h.

◆ DWT_CTRL_NOPRFCNT_Pos [8/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 939 of file core_cm4.h.

◆ DWT_CTRL_NOPRFCNT_Pos [9/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 1162 of file core_cm7.h.

◆ DWT_CTRL_NOPRFCNT_Pos [10/10]

#define DWT_CTRL_NOPRFCNT_Pos 24U

DWT CTRL: NOPRFCNT Position

Definition at line 866 of file core_sc300.h.

◆ DWT_CTRL_NOTRCPKT_Msk [1/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 1286 of file core_armv81mml.h.

◆ DWT_CTRL_NOTRCPKT_Msk [2/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 685 of file core_armv8mbl.h.

◆ DWT_CTRL_NOTRCPKT_Msk [3/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 1190 of file core_armv8mml.h.

◆ DWT_CTRL_NOTRCPKT_Msk [4/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 685 of file core_cm23.h.

◆ DWT_CTRL_NOTRCPKT_Msk [5/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 873 of file core_cm3.h.

◆ DWT_CTRL_NOTRCPKT_Msk [6/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 1190 of file core_cm33.h.

◆ DWT_CTRL_NOTRCPKT_Msk [7/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 1190 of file core_cm35p.h.

◆ DWT_CTRL_NOTRCPKT_Msk [8/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 931 of file core_cm4.h.

◆ DWT_CTRL_NOTRCPKT_Msk [9/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 1154 of file core_cm7.h.

◆ DWT_CTRL_NOTRCPKT_Msk [10/10]

#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)

DWT CTRL: NOTRCPKT Mask

Definition at line 858 of file core_sc300.h.

◆ DWT_CTRL_NOTRCPKT_Pos [1/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 1285 of file core_armv81mml.h.

◆ DWT_CTRL_NOTRCPKT_Pos [2/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 684 of file core_armv8mbl.h.

◆ DWT_CTRL_NOTRCPKT_Pos [3/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 1189 of file core_armv8mml.h.

◆ DWT_CTRL_NOTRCPKT_Pos [4/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 684 of file core_cm23.h.

◆ DWT_CTRL_NOTRCPKT_Pos [5/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 872 of file core_cm3.h.

◆ DWT_CTRL_NOTRCPKT_Pos [6/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 1189 of file core_cm33.h.

◆ DWT_CTRL_NOTRCPKT_Pos [7/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 1189 of file core_cm35p.h.

◆ DWT_CTRL_NOTRCPKT_Pos [8/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 930 of file core_cm4.h.

◆ DWT_CTRL_NOTRCPKT_Pos [9/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 1153 of file core_cm7.h.

◆ DWT_CTRL_NOTRCPKT_Pos [10/10]

#define DWT_CTRL_NOTRCPKT_Pos 27U

DWT CTRL: NOTRCPKT Position

Definition at line 857 of file core_sc300.h.

◆ DWT_CTRL_NUMCOMP_Msk [1/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 1283 of file core_armv81mml.h.

◆ DWT_CTRL_NUMCOMP_Msk [2/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 682 of file core_armv8mbl.h.

◆ DWT_CTRL_NUMCOMP_Msk [3/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 1187 of file core_armv8mml.h.

◆ DWT_CTRL_NUMCOMP_Msk [4/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 682 of file core_cm23.h.

◆ DWT_CTRL_NUMCOMP_Msk [5/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 870 of file core_cm3.h.

◆ DWT_CTRL_NUMCOMP_Msk [6/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 1187 of file core_cm33.h.

◆ DWT_CTRL_NUMCOMP_Msk [7/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 1187 of file core_cm35p.h.

◆ DWT_CTRL_NUMCOMP_Msk [8/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 928 of file core_cm4.h.

◆ DWT_CTRL_NUMCOMP_Msk [9/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 1151 of file core_cm7.h.

◆ DWT_CTRL_NUMCOMP_Msk [10/10]

#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)

DWT CTRL: NUMCOMP Mask

Definition at line 855 of file core_sc300.h.

◆ DWT_CTRL_NUMCOMP_Pos [1/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 1282 of file core_armv81mml.h.

◆ DWT_CTRL_NUMCOMP_Pos [2/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 681 of file core_armv8mbl.h.

◆ DWT_CTRL_NUMCOMP_Pos [3/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 1186 of file core_armv8mml.h.

◆ DWT_CTRL_NUMCOMP_Pos [4/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 681 of file core_cm23.h.

◆ DWT_CTRL_NUMCOMP_Pos [5/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 869 of file core_cm3.h.

◆ DWT_CTRL_NUMCOMP_Pos [6/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 1186 of file core_cm33.h.

◆ DWT_CTRL_NUMCOMP_Pos [7/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 1186 of file core_cm35p.h.

◆ DWT_CTRL_NUMCOMP_Pos [8/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 927 of file core_cm4.h.

◆ DWT_CTRL_NUMCOMP_Pos [9/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 1150 of file core_cm7.h.

◆ DWT_CTRL_NUMCOMP_Pos [10/10]

#define DWT_CTRL_NUMCOMP_Pos 28U

DWT CTRL: NUMCOMP Position

Definition at line 854 of file core_sc300.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [1/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 1322 of file core_armv81mml.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [2/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 1226 of file core_armv8mml.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [3/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 906 of file core_cm3.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [4/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 1226 of file core_cm33.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [5/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 1226 of file core_cm35p.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [6/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 964 of file core_cm4.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [7/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 1187 of file core_cm7.h.

◆ DWT_CTRL_PCSAMPLENA_Msk [8/8]

#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)

DWT CTRL: PCSAMPLENA Mask

Definition at line 891 of file core_sc300.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [1/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 1321 of file core_armv81mml.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [2/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 1225 of file core_armv8mml.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [3/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 905 of file core_cm3.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [4/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 1225 of file core_cm33.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [5/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 1225 of file core_cm35p.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [6/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 963 of file core_cm4.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [7/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 1186 of file core_cm7.h.

◆ DWT_CTRL_PCSAMPLENA_Pos [8/8]

#define DWT_CTRL_PCSAMPLENA_Pos 12U

DWT CTRL: PCSAMPLENA Position

Definition at line 890 of file core_sc300.h.

◆ DWT_CTRL_POSTINIT_Msk [1/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 1331 of file core_armv81mml.h.

◆ DWT_CTRL_POSTINIT_Msk [2/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 1235 of file core_armv8mml.h.

◆ DWT_CTRL_POSTINIT_Msk [3/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 915 of file core_cm3.h.

◆ DWT_CTRL_POSTINIT_Msk [4/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 1235 of file core_cm33.h.

◆ DWT_CTRL_POSTINIT_Msk [5/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 1235 of file core_cm35p.h.

◆ DWT_CTRL_POSTINIT_Msk [6/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 973 of file core_cm4.h.

◆ DWT_CTRL_POSTINIT_Msk [7/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 1196 of file core_cm7.h.

◆ DWT_CTRL_POSTINIT_Msk [8/8]

#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)

DWT CTRL: POSTINIT Mask

Definition at line 900 of file core_sc300.h.

◆ DWT_CTRL_POSTINIT_Pos [1/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 1330 of file core_armv81mml.h.

◆ DWT_CTRL_POSTINIT_Pos [2/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 1234 of file core_armv8mml.h.

◆ DWT_CTRL_POSTINIT_Pos [3/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 914 of file core_cm3.h.

◆ DWT_CTRL_POSTINIT_Pos [4/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 1234 of file core_cm33.h.

◆ DWT_CTRL_POSTINIT_Pos [5/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 1234 of file core_cm35p.h.

◆ DWT_CTRL_POSTINIT_Pos [6/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 972 of file core_cm4.h.

◆ DWT_CTRL_POSTINIT_Pos [7/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 1195 of file core_cm7.h.

◆ DWT_CTRL_POSTINIT_Pos [8/8]

#define DWT_CTRL_POSTINIT_Pos 5U

DWT CTRL: POSTINIT Position

Definition at line 899 of file core_sc300.h.

◆ DWT_CTRL_POSTPRESET_Msk [1/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 1334 of file core_armv81mml.h.

◆ DWT_CTRL_POSTPRESET_Msk [2/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 1238 of file core_armv8mml.h.

◆ DWT_CTRL_POSTPRESET_Msk [3/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 918 of file core_cm3.h.

◆ DWT_CTRL_POSTPRESET_Msk [4/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 1238 of file core_cm33.h.

◆ DWT_CTRL_POSTPRESET_Msk [5/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 1238 of file core_cm35p.h.

◆ DWT_CTRL_POSTPRESET_Msk [6/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 976 of file core_cm4.h.

◆ DWT_CTRL_POSTPRESET_Msk [7/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 1199 of file core_cm7.h.

◆ DWT_CTRL_POSTPRESET_Msk [8/8]

#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)

DWT CTRL: POSTPRESET Mask

Definition at line 903 of file core_sc300.h.

◆ DWT_CTRL_POSTPRESET_Pos [1/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 1333 of file core_armv81mml.h.

◆ DWT_CTRL_POSTPRESET_Pos [2/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 1237 of file core_armv8mml.h.

◆ DWT_CTRL_POSTPRESET_Pos [3/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 917 of file core_cm3.h.

◆ DWT_CTRL_POSTPRESET_Pos [4/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 1237 of file core_cm33.h.

◆ DWT_CTRL_POSTPRESET_Pos [5/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 1237 of file core_cm35p.h.

◆ DWT_CTRL_POSTPRESET_Pos [6/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 975 of file core_cm4.h.

◆ DWT_CTRL_POSTPRESET_Pos [7/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 1198 of file core_cm7.h.

◆ DWT_CTRL_POSTPRESET_Pos [8/8]

#define DWT_CTRL_POSTPRESET_Pos 1U

DWT CTRL: POSTPRESET Position

Definition at line 902 of file core_sc300.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [1/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 1310 of file core_armv81mml.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [2/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 1214 of file core_armv8mml.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [3/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 894 of file core_cm3.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [4/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 1214 of file core_cm33.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [5/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 1214 of file core_cm35p.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [6/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 952 of file core_cm4.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [7/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 1175 of file core_cm7.h.

◆ DWT_CTRL_SLEEPEVTENA_Msk [8/8]

#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)

DWT CTRL: SLEEPEVTENA Mask

Definition at line 879 of file core_sc300.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [1/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 1309 of file core_armv81mml.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [2/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 1213 of file core_armv8mml.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [3/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 893 of file core_cm3.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [4/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 1213 of file core_cm33.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [5/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 1213 of file core_cm35p.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [6/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 951 of file core_cm4.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [7/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 1174 of file core_cm7.h.

◆ DWT_CTRL_SLEEPEVTENA_Pos [8/8]

#define DWT_CTRL_SLEEPEVTENA_Pos 19U

DWT CTRL: SLEEPEVTENA Position

Definition at line 878 of file core_sc300.h.

◆ DWT_CTRL_SYNCTAP_Msk [1/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 1325 of file core_armv81mml.h.

◆ DWT_CTRL_SYNCTAP_Msk [2/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 1229 of file core_armv8mml.h.

◆ DWT_CTRL_SYNCTAP_Msk [3/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 909 of file core_cm3.h.

◆ DWT_CTRL_SYNCTAP_Msk [4/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 1229 of file core_cm33.h.

◆ DWT_CTRL_SYNCTAP_Msk [5/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 1229 of file core_cm35p.h.

◆ DWT_CTRL_SYNCTAP_Msk [6/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 967 of file core_cm4.h.

◆ DWT_CTRL_SYNCTAP_Msk [7/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 1190 of file core_cm7.h.

◆ DWT_CTRL_SYNCTAP_Msk [8/8]

#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)

DWT CTRL: SYNCTAP Mask

Definition at line 894 of file core_sc300.h.

◆ DWT_CTRL_SYNCTAP_Pos [1/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 1324 of file core_armv81mml.h.

◆ DWT_CTRL_SYNCTAP_Pos [2/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 1228 of file core_armv8mml.h.

◆ DWT_CTRL_SYNCTAP_Pos [3/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 908 of file core_cm3.h.

◆ DWT_CTRL_SYNCTAP_Pos [4/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 1228 of file core_cm33.h.

◆ DWT_CTRL_SYNCTAP_Pos [5/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 1228 of file core_cm35p.h.

◆ DWT_CTRL_SYNCTAP_Pos [6/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 966 of file core_cm4.h.

◆ DWT_CTRL_SYNCTAP_Pos [7/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 1189 of file core_cm7.h.

◆ DWT_CTRL_SYNCTAP_Pos [8/8]

#define DWT_CTRL_SYNCTAP_Pos 10U

DWT CTRL: SYNCTAP Position

Definition at line 893 of file core_sc300.h.

◆ DWT_EXCCNT_EXCCNT_Msk [1/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 1345 of file core_armv81mml.h.

◆ DWT_EXCCNT_EXCCNT_Msk [2/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 1249 of file core_armv8mml.h.

◆ DWT_EXCCNT_EXCCNT_Msk [3/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 929 of file core_cm3.h.

◆ DWT_EXCCNT_EXCCNT_Msk [4/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 1249 of file core_cm33.h.

◆ DWT_EXCCNT_EXCCNT_Msk [5/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 1249 of file core_cm35p.h.

◆ DWT_EXCCNT_EXCCNT_Msk [6/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 987 of file core_cm4.h.

◆ DWT_EXCCNT_EXCCNT_Msk [7/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 1210 of file core_cm7.h.

◆ DWT_EXCCNT_EXCCNT_Msk [8/8]

#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)

DWT EXCCNT: EXCCNT Mask

Definition at line 914 of file core_sc300.h.

◆ DWT_EXCCNT_EXCCNT_Pos [1/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 1344 of file core_armv81mml.h.

◆ DWT_EXCCNT_EXCCNT_Pos [2/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 1248 of file core_armv8mml.h.

◆ DWT_EXCCNT_EXCCNT_Pos [3/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 928 of file core_cm3.h.

◆ DWT_EXCCNT_EXCCNT_Pos [4/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 1248 of file core_cm33.h.

◆ DWT_EXCCNT_EXCCNT_Pos [5/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 1248 of file core_cm35p.h.

◆ DWT_EXCCNT_EXCCNT_Pos [6/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 986 of file core_cm4.h.

◆ DWT_EXCCNT_EXCCNT_Pos [7/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 1209 of file core_cm7.h.

◆ DWT_EXCCNT_EXCCNT_Pos [8/8]

#define DWT_EXCCNT_EXCCNT_Pos 0U

DWT EXCCNT: EXCCNT Position

Definition at line 913 of file core_sc300.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [1/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 1357 of file core_armv81mml.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [2/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 1261 of file core_armv8mml.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [3/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 941 of file core_cm3.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [4/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 1261 of file core_cm33.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [5/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 1261 of file core_cm35p.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [6/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 999 of file core_cm4.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [7/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 1222 of file core_cm7.h.

◆ DWT_FOLDCNT_FOLDCNT_Msk [8/8]

#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)

DWT FOLDCNT: FOLDCNT Mask

Definition at line 926 of file core_sc300.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [1/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 1356 of file core_armv81mml.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [2/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 1260 of file core_armv8mml.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [3/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 940 of file core_cm3.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [4/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 1260 of file core_cm33.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [5/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 1260 of file core_cm35p.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [6/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 998 of file core_cm4.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [7/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 1221 of file core_cm7.h.

◆ DWT_FOLDCNT_FOLDCNT_Pos [8/8]

#define DWT_FOLDCNT_FOLDCNT_Pos 0U

DWT FOLDCNT: FOLDCNT Position

Definition at line 925 of file core_sc300.h.

◆ DWT_FUNCTION_ACTION_Msk [1/6]

#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

DWT FUNCTION: ACTION Mask

Definition at line 1370 of file core_armv81mml.h.

◆ DWT_FUNCTION_ACTION_Msk [2/6]

#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)

DWT FUNCTION: ACTION Mask

Definition at line 707 of file core_armv8mbl.h.

◆ DWT_FUNCTION_ACTION_Msk [3/6]

#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

DWT FUNCTION: ACTION Mask

Definition at line 1274 of file core_armv8mml.h.

◆ DWT_FUNCTION_ACTION_Msk [4/6]

#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos)

DWT FUNCTION: ACTION Mask

Definition at line 707 of file core_cm23.h.

◆ DWT_FUNCTION_ACTION_Msk [5/6]

#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

DWT FUNCTION: ACTION Mask

Definition at line 1274 of file core_cm33.h.

◆ DWT_FUNCTION_ACTION_Msk [6/6]

#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)

DWT FUNCTION: ACTION Mask

Definition at line 1274 of file core_cm35p.h.

◆ DWT_FUNCTION_ACTION_Pos [1/6]

#define DWT_FUNCTION_ACTION_Pos 4U

DWT FUNCTION: ACTION Position

Definition at line 1369 of file core_armv81mml.h.

◆ DWT_FUNCTION_ACTION_Pos [2/6]

#define DWT_FUNCTION_ACTION_Pos 4U

DWT FUNCTION: ACTION Position

Definition at line 706 of file core_armv8mbl.h.

◆ DWT_FUNCTION_ACTION_Pos [3/6]

#define DWT_FUNCTION_ACTION_Pos 4U

DWT FUNCTION: ACTION Position

Definition at line 1273 of file core_armv8mml.h.

◆ DWT_FUNCTION_ACTION_Pos [4/6]

#define DWT_FUNCTION_ACTION_Pos 4U

DWT FUNCTION: ACTION Position

Definition at line 706 of file core_cm23.h.

◆ DWT_FUNCTION_ACTION_Pos [5/6]

#define DWT_FUNCTION_ACTION_Pos 4U

DWT FUNCTION: ACTION Position

Definition at line 1273 of file core_cm33.h.

◆ DWT_FUNCTION_ACTION_Pos [6/6]

#define DWT_FUNCTION_ACTION_Pos 4U

DWT FUNCTION: ACTION Position

Definition at line 1273 of file core_cm35p.h.

◆ DWT_FUNCTION_CYCMATCH_Msk [1/4]

#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

Definition at line 967 of file core_cm3.h.

◆ DWT_FUNCTION_CYCMATCH_Msk [2/4]

#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

Definition at line 1025 of file core_cm4.h.

◆ DWT_FUNCTION_CYCMATCH_Msk [3/4]

#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

Definition at line 1248 of file core_cm7.h.

◆ DWT_FUNCTION_CYCMATCH_Msk [4/4]

#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)

DWT FUNCTION: CYCMATCH Mask

Definition at line 952 of file core_sc300.h.

◆ DWT_FUNCTION_CYCMATCH_Pos [1/4]

#define DWT_FUNCTION_CYCMATCH_Pos 7U

DWT FUNCTION: CYCMATCH Position

Definition at line 966 of file core_cm3.h.

◆ DWT_FUNCTION_CYCMATCH_Pos [2/4]

#define DWT_FUNCTION_CYCMATCH_Pos 7U

DWT FUNCTION: CYCMATCH Position

Definition at line 1024 of file core_cm4.h.

◆ DWT_FUNCTION_CYCMATCH_Pos [3/4]

#define DWT_FUNCTION_CYCMATCH_Pos 7U

DWT FUNCTION: CYCMATCH Position

Definition at line 1247 of file core_cm7.h.

◆ DWT_FUNCTION_CYCMATCH_Pos [4/4]

#define DWT_FUNCTION_CYCMATCH_Pos 7U

DWT FUNCTION: CYCMATCH Position

Definition at line 951 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVADDR0_Msk [1/4]

#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

Definition at line 955 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVADDR0_Msk [2/4]

#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

Definition at line 1013 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVADDR0_Msk [3/4]

#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

Definition at line 1236 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVADDR0_Msk [4/4]

#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)

DWT FUNCTION: DATAVADDR0 Mask

Definition at line 940 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVADDR0_Pos [1/4]

#define DWT_FUNCTION_DATAVADDR0_Pos 12U

DWT FUNCTION: DATAVADDR0 Position

Definition at line 954 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVADDR0_Pos [2/4]

#define DWT_FUNCTION_DATAVADDR0_Pos 12U

DWT FUNCTION: DATAVADDR0 Position

Definition at line 1012 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVADDR0_Pos [3/4]

#define DWT_FUNCTION_DATAVADDR0_Pos 12U

DWT FUNCTION: DATAVADDR0 Position

Definition at line 1235 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVADDR0_Pos [4/4]

#define DWT_FUNCTION_DATAVADDR0_Pos 12U

DWT FUNCTION: DATAVADDR0 Position

Definition at line 939 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVADDR1_Msk [1/4]

#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

Definition at line 952 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVADDR1_Msk [2/4]

#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

Definition at line 1010 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVADDR1_Msk [3/4]

#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

Definition at line 1233 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVADDR1_Msk [4/4]

#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)

DWT FUNCTION: DATAVADDR1 Mask

Definition at line 937 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVADDR1_Pos [1/4]

#define DWT_FUNCTION_DATAVADDR1_Pos 16U

DWT FUNCTION: DATAVADDR1 Position

Definition at line 951 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVADDR1_Pos [2/4]

#define DWT_FUNCTION_DATAVADDR1_Pos 16U

DWT FUNCTION: DATAVADDR1 Position

Definition at line 1009 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVADDR1_Pos [3/4]

#define DWT_FUNCTION_DATAVADDR1_Pos 16U

DWT FUNCTION: DATAVADDR1 Position

Definition at line 1232 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVADDR1_Pos [4/4]

#define DWT_FUNCTION_DATAVADDR1_Pos 16U

DWT FUNCTION: DATAVADDR1 Position

Definition at line 936 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVMATCH_Msk [1/4]

#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

Definition at line 964 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVMATCH_Msk [2/4]

#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

Definition at line 1022 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVMATCH_Msk [3/4]

#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

Definition at line 1245 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVMATCH_Msk [4/4]

#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)

DWT FUNCTION: DATAVMATCH Mask

Definition at line 949 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVMATCH_Pos [1/4]

#define DWT_FUNCTION_DATAVMATCH_Pos 8U

DWT FUNCTION: DATAVMATCH Position

Definition at line 963 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVMATCH_Pos [2/4]

#define DWT_FUNCTION_DATAVMATCH_Pos 8U

DWT FUNCTION: DATAVMATCH Position

Definition at line 1021 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVMATCH_Pos [3/4]

#define DWT_FUNCTION_DATAVMATCH_Pos 8U

DWT FUNCTION: DATAVMATCH Position

Definition at line 1244 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVMATCH_Pos [4/4]

#define DWT_FUNCTION_DATAVMATCH_Pos 8U

DWT FUNCTION: DATAVMATCH Position

Definition at line 948 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [1/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 1367 of file core_armv81mml.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [2/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 704 of file core_armv8mbl.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [3/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 1271 of file core_armv8mml.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [4/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 704 of file core_cm23.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [5/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 958 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [6/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 1271 of file core_cm33.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [7/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 1271 of file core_cm35p.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [8/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 1016 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [9/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 1239 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVSIZE_Msk [10/10]

#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)

DWT FUNCTION: DATAVSIZE Mask

Definition at line 943 of file core_sc300.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [1/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 1366 of file core_armv81mml.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [2/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 703 of file core_armv8mbl.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [3/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 1270 of file core_armv8mml.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [4/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 703 of file core_cm23.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [5/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 957 of file core_cm3.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [6/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 1270 of file core_cm33.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [7/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 1270 of file core_cm35p.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [8/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 1015 of file core_cm4.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [9/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 1238 of file core_cm7.h.

◆ DWT_FUNCTION_DATAVSIZE_Pos [10/10]

#define DWT_FUNCTION_DATAVSIZE_Pos 10U

DWT FUNCTION: DATAVSIZE Position

Definition at line 942 of file core_sc300.h.

◆ DWT_FUNCTION_EMITRANGE_Msk [1/4]

#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

Definition at line 970 of file core_cm3.h.

◆ DWT_FUNCTION_EMITRANGE_Msk [2/4]

#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

Definition at line 1028 of file core_cm4.h.

◆ DWT_FUNCTION_EMITRANGE_Msk [3/4]

#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

Definition at line 1251 of file core_cm7.h.

◆ DWT_FUNCTION_EMITRANGE_Msk [4/4]

#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)

DWT FUNCTION: EMITRANGE Mask

Definition at line 955 of file core_sc300.h.

◆ DWT_FUNCTION_EMITRANGE_Pos [1/4]

#define DWT_FUNCTION_EMITRANGE_Pos 5U

DWT FUNCTION: EMITRANGE Position

Definition at line 969 of file core_cm3.h.

◆ DWT_FUNCTION_EMITRANGE_Pos [2/4]

#define DWT_FUNCTION_EMITRANGE_Pos 5U

DWT FUNCTION: EMITRANGE Position

Definition at line 1027 of file core_cm4.h.

◆ DWT_FUNCTION_EMITRANGE_Pos [3/4]

#define DWT_FUNCTION_EMITRANGE_Pos 5U

DWT FUNCTION: EMITRANGE Position

Definition at line 1250 of file core_cm7.h.

◆ DWT_FUNCTION_EMITRANGE_Pos [4/4]

#define DWT_FUNCTION_EMITRANGE_Pos 5U

DWT FUNCTION: EMITRANGE Position

Definition at line 954 of file core_sc300.h.

◆ DWT_FUNCTION_FUNCTION_Msk [1/4]

#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

Definition at line 973 of file core_cm3.h.

◆ DWT_FUNCTION_FUNCTION_Msk [2/4]

#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

Definition at line 1031 of file core_cm4.h.

◆ DWT_FUNCTION_FUNCTION_Msk [3/4]

#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

Definition at line 1254 of file core_cm7.h.

◆ DWT_FUNCTION_FUNCTION_Msk [4/4]

#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)

DWT FUNCTION: FUNCTION Mask

Definition at line 958 of file core_sc300.h.

◆ DWT_FUNCTION_FUNCTION_Pos [1/4]

#define DWT_FUNCTION_FUNCTION_Pos 0U

DWT FUNCTION: FUNCTION Position

Definition at line 972 of file core_cm3.h.

◆ DWT_FUNCTION_FUNCTION_Pos [2/4]

#define DWT_FUNCTION_FUNCTION_Pos 0U

DWT FUNCTION: FUNCTION Position

Definition at line 1030 of file core_cm4.h.

◆ DWT_FUNCTION_FUNCTION_Pos [3/4]

#define DWT_FUNCTION_FUNCTION_Pos 0U

DWT FUNCTION: FUNCTION Position

Definition at line 1253 of file core_cm7.h.

◆ DWT_FUNCTION_FUNCTION_Pos [4/4]

#define DWT_FUNCTION_FUNCTION_Pos 0U

DWT FUNCTION: FUNCTION Position

Definition at line 957 of file core_sc300.h.

◆ DWT_FUNCTION_ID_Msk [1/6]

#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

DWT FUNCTION: ID Mask

Definition at line 1361 of file core_armv81mml.h.

◆ DWT_FUNCTION_ID_Msk [2/6]

#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

DWT FUNCTION: ID Mask

Definition at line 698 of file core_armv8mbl.h.

◆ DWT_FUNCTION_ID_Msk [3/6]

#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

DWT FUNCTION: ID Mask

Definition at line 1265 of file core_armv8mml.h.

◆ DWT_FUNCTION_ID_Msk [4/6]

#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

DWT FUNCTION: ID Mask

Definition at line 698 of file core_cm23.h.

◆ DWT_FUNCTION_ID_Msk [5/6]

#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

DWT FUNCTION: ID Mask

Definition at line 1265 of file core_cm33.h.

◆ DWT_FUNCTION_ID_Msk [6/6]

#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)

DWT FUNCTION: ID Mask

Definition at line 1265 of file core_cm35p.h.

◆ DWT_FUNCTION_ID_Pos [1/6]

#define DWT_FUNCTION_ID_Pos 27U

DWT FUNCTION: ID Position

Definition at line 1360 of file core_armv81mml.h.

◆ DWT_FUNCTION_ID_Pos [2/6]

#define DWT_FUNCTION_ID_Pos 27U

DWT FUNCTION: ID Position

Definition at line 697 of file core_armv8mbl.h.

◆ DWT_FUNCTION_ID_Pos [3/6]

#define DWT_FUNCTION_ID_Pos 27U

DWT FUNCTION: ID Position

Definition at line 1264 of file core_armv8mml.h.

◆ DWT_FUNCTION_ID_Pos [4/6]

#define DWT_FUNCTION_ID_Pos 27U

DWT FUNCTION: ID Position

Definition at line 697 of file core_cm23.h.

◆ DWT_FUNCTION_ID_Pos [5/6]

#define DWT_FUNCTION_ID_Pos 27U

DWT FUNCTION: ID Position

Definition at line 1264 of file core_cm33.h.

◆ DWT_FUNCTION_ID_Pos [6/6]

#define DWT_FUNCTION_ID_Pos 27U

DWT FUNCTION: ID Position

Definition at line 1264 of file core_cm35p.h.

◆ DWT_FUNCTION_LNK1ENA_Msk [1/4]

#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

Definition at line 961 of file core_cm3.h.

◆ DWT_FUNCTION_LNK1ENA_Msk [2/4]

#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

Definition at line 1019 of file core_cm4.h.

◆ DWT_FUNCTION_LNK1ENA_Msk [3/4]

#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

Definition at line 1242 of file core_cm7.h.

◆ DWT_FUNCTION_LNK1ENA_Msk [4/4]

#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)

DWT FUNCTION: LNK1ENA Mask

Definition at line 946 of file core_sc300.h.

◆ DWT_FUNCTION_LNK1ENA_Pos [1/4]

#define DWT_FUNCTION_LNK1ENA_Pos 9U

DWT FUNCTION: LNK1ENA Position

Definition at line 960 of file core_cm3.h.

◆ DWT_FUNCTION_LNK1ENA_Pos [2/4]

#define DWT_FUNCTION_LNK1ENA_Pos 9U

DWT FUNCTION: LNK1ENA Position

Definition at line 1018 of file core_cm4.h.

◆ DWT_FUNCTION_LNK1ENA_Pos [3/4]

#define DWT_FUNCTION_LNK1ENA_Pos 9U

DWT FUNCTION: LNK1ENA Position

Definition at line 1241 of file core_cm7.h.

◆ DWT_FUNCTION_LNK1ENA_Pos [4/4]

#define DWT_FUNCTION_LNK1ENA_Pos 9U

DWT FUNCTION: LNK1ENA Position

Definition at line 945 of file core_sc300.h.

◆ DWT_FUNCTION_MATCH_Msk [1/6]

#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)

DWT FUNCTION: MATCH Mask

Definition at line 1373 of file core_armv81mml.h.

◆ DWT_FUNCTION_MATCH_Msk [2/6]

#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)

DWT FUNCTION: MATCH Mask

Definition at line 710 of file core_armv8mbl.h.

◆ DWT_FUNCTION_MATCH_Msk [3/6]

#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)

DWT FUNCTION: MATCH Mask

Definition at line 1277 of file core_armv8mml.h.

◆ DWT_FUNCTION_MATCH_Msk [4/6]

#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)

DWT FUNCTION: MATCH Mask

Definition at line 710 of file core_cm23.h.

◆ DWT_FUNCTION_MATCH_Msk [5/6]

#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)

DWT FUNCTION: MATCH Mask

Definition at line 1277 of file core_cm33.h.

◆ DWT_FUNCTION_MATCH_Msk [6/6]

#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)

DWT FUNCTION: MATCH Mask

Definition at line 1277 of file core_cm35p.h.

◆ DWT_FUNCTION_MATCH_Pos [1/6]

#define DWT_FUNCTION_MATCH_Pos 0U

DWT FUNCTION: MATCH Position

Definition at line 1372 of file core_armv81mml.h.

◆ DWT_FUNCTION_MATCH_Pos [2/6]

#define DWT_FUNCTION_MATCH_Pos 0U

DWT FUNCTION: MATCH Position

Definition at line 709 of file core_armv8mbl.h.

◆ DWT_FUNCTION_MATCH_Pos [3/6]

#define DWT_FUNCTION_MATCH_Pos 0U

DWT FUNCTION: MATCH Position

Definition at line 1276 of file core_armv8mml.h.

◆ DWT_FUNCTION_MATCH_Pos [4/6]

#define DWT_FUNCTION_MATCH_Pos 0U

DWT FUNCTION: MATCH Position

Definition at line 709 of file core_cm23.h.

◆ DWT_FUNCTION_MATCH_Pos [5/6]

#define DWT_FUNCTION_MATCH_Pos 0U

DWT FUNCTION: MATCH Position

Definition at line 1276 of file core_cm33.h.

◆ DWT_FUNCTION_MATCH_Pos [6/6]

#define DWT_FUNCTION_MATCH_Pos 0U

DWT FUNCTION: MATCH Position

Definition at line 1276 of file core_cm35p.h.

◆ DWT_FUNCTION_MATCHED_Msk [1/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 1364 of file core_armv81mml.h.

◆ DWT_FUNCTION_MATCHED_Msk [2/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 701 of file core_armv8mbl.h.

◆ DWT_FUNCTION_MATCHED_Msk [3/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 1268 of file core_armv8mml.h.

◆ DWT_FUNCTION_MATCHED_Msk [4/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 701 of file core_cm23.h.

◆ DWT_FUNCTION_MATCHED_Msk [5/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 949 of file core_cm3.h.

◆ DWT_FUNCTION_MATCHED_Msk [6/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 1268 of file core_cm33.h.

◆ DWT_FUNCTION_MATCHED_Msk [7/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 1268 of file core_cm35p.h.

◆ DWT_FUNCTION_MATCHED_Msk [8/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 1007 of file core_cm4.h.

◆ DWT_FUNCTION_MATCHED_Msk [9/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 1230 of file core_cm7.h.

◆ DWT_FUNCTION_MATCHED_Msk [10/10]

#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)

DWT FUNCTION: MATCHED Mask

Definition at line 934 of file core_sc300.h.

◆ DWT_FUNCTION_MATCHED_Pos [1/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 1363 of file core_armv81mml.h.

◆ DWT_FUNCTION_MATCHED_Pos [2/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 700 of file core_armv8mbl.h.

◆ DWT_FUNCTION_MATCHED_Pos [3/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 1267 of file core_armv8mml.h.

◆ DWT_FUNCTION_MATCHED_Pos [4/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 700 of file core_cm23.h.

◆ DWT_FUNCTION_MATCHED_Pos [5/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 948 of file core_cm3.h.

◆ DWT_FUNCTION_MATCHED_Pos [6/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 1267 of file core_cm33.h.

◆ DWT_FUNCTION_MATCHED_Pos [7/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 1267 of file core_cm35p.h.

◆ DWT_FUNCTION_MATCHED_Pos [8/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 1006 of file core_cm4.h.

◆ DWT_FUNCTION_MATCHED_Pos [9/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 1229 of file core_cm7.h.

◆ DWT_FUNCTION_MATCHED_Pos [10/10]

#define DWT_FUNCTION_MATCHED_Pos 24U

DWT FUNCTION: MATCHED Position

Definition at line 933 of file core_sc300.h.

◆ DWT_LSUCNT_LSUCNT_Msk [1/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 1353 of file core_armv81mml.h.

◆ DWT_LSUCNT_LSUCNT_Msk [2/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 1257 of file core_armv8mml.h.

◆ DWT_LSUCNT_LSUCNT_Msk [3/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 937 of file core_cm3.h.

◆ DWT_LSUCNT_LSUCNT_Msk [4/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 1257 of file core_cm33.h.

◆ DWT_LSUCNT_LSUCNT_Msk [5/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 1257 of file core_cm35p.h.

◆ DWT_LSUCNT_LSUCNT_Msk [6/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 995 of file core_cm4.h.

◆ DWT_LSUCNT_LSUCNT_Msk [7/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 1218 of file core_cm7.h.

◆ DWT_LSUCNT_LSUCNT_Msk [8/8]

#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)

DWT LSUCNT: LSUCNT Mask

Definition at line 922 of file core_sc300.h.

◆ DWT_LSUCNT_LSUCNT_Pos [1/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 1352 of file core_armv81mml.h.

◆ DWT_LSUCNT_LSUCNT_Pos [2/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 1256 of file core_armv8mml.h.

◆ DWT_LSUCNT_LSUCNT_Pos [3/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 936 of file core_cm3.h.

◆ DWT_LSUCNT_LSUCNT_Pos [4/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 1256 of file core_cm33.h.

◆ DWT_LSUCNT_LSUCNT_Pos [5/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 1256 of file core_cm35p.h.

◆ DWT_LSUCNT_LSUCNT_Pos [6/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 994 of file core_cm4.h.

◆ DWT_LSUCNT_LSUCNT_Pos [7/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 1217 of file core_cm7.h.

◆ DWT_LSUCNT_LSUCNT_Pos [8/8]

#define DWT_LSUCNT_LSUCNT_Pos 0U

DWT LSUCNT: LSUCNT Position

Definition at line 921 of file core_sc300.h.

◆ DWT_MASK_MASK_Msk [1/4]

#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

Definition at line 945 of file core_cm3.h.

◆ DWT_MASK_MASK_Msk [2/4]

#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

Definition at line 1003 of file core_cm4.h.

◆ DWT_MASK_MASK_Msk [3/4]

#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

Definition at line 1226 of file core_cm7.h.

◆ DWT_MASK_MASK_Msk [4/4]

#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)

DWT MASK: MASK Mask

Definition at line 930 of file core_sc300.h.

◆ DWT_MASK_MASK_Pos [1/4]

#define DWT_MASK_MASK_Pos 0U

DWT MASK: MASK Position

Definition at line 944 of file core_cm3.h.

◆ DWT_MASK_MASK_Pos [2/4]

#define DWT_MASK_MASK_Pos 0U

DWT MASK: MASK Position

Definition at line 1002 of file core_cm4.h.

◆ DWT_MASK_MASK_Pos [3/4]

#define DWT_MASK_MASK_Pos 0U

DWT MASK: MASK Position

Definition at line 1225 of file core_cm7.h.

◆ DWT_MASK_MASK_Pos [4/4]

#define DWT_MASK_MASK_Pos 0U

DWT MASK: MASK Position

Definition at line 929 of file core_sc300.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [1/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 1349 of file core_armv81mml.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [2/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 1253 of file core_armv8mml.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [3/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 933 of file core_cm3.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [4/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 1253 of file core_cm33.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [5/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 1253 of file core_cm35p.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [6/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 991 of file core_cm4.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [7/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 1214 of file core_cm7.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Msk [8/8]

#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)

DWT SLEEPCNT: SLEEPCNT Mask

Definition at line 918 of file core_sc300.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [1/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 1348 of file core_armv81mml.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [2/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 1252 of file core_armv8mml.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [3/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 932 of file core_cm3.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [4/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 1252 of file core_cm33.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [5/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 1252 of file core_cm35p.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [6/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 990 of file core_cm4.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [7/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 1213 of file core_cm7.h.

◆ DWT_SLEEPCNT_SLEEPCNT_Pos [8/8]

#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U

DWT SLEEPCNT: SLEEPCNT Position

Definition at line 917 of file core_sc300.h.

◆ EXC_INTEGRITY_SIGNATURE [1/5]

#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

Definition at line 1233 of file core_armv8mbl.h.

◆ EXC_INTEGRITY_SIGNATURE [2/5]

#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

Definition at line 2008 of file core_armv8mml.h.

◆ EXC_INTEGRITY_SIGNATURE [3/5]

#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

Definition at line 1308 of file core_cm23.h.

◆ EXC_INTEGRITY_SIGNATURE [4/5]

#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

Definition at line 2083 of file core_cm33.h.

◆ EXC_INTEGRITY_SIGNATURE [5/5]

#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */

Definition at line 2083 of file core_cm35p.h.

◆ EXC_RETURN_DCRS [1/5]

#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

Definition at line 1223 of file core_armv8mbl.h.

◆ EXC_RETURN_DCRS [2/5]

#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

Definition at line 1998 of file core_armv8mml.h.

◆ EXC_RETURN_DCRS [3/5]

#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

Definition at line 1298 of file core_cm23.h.

◆ EXC_RETURN_DCRS [4/5]

#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

Definition at line 2073 of file core_cm33.h.

◆ EXC_RETURN_DCRS [5/5]

#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */

Definition at line 2073 of file core_cm35p.h.

◆ EXC_RETURN_ES [1/5]

#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

Definition at line 1227 of file core_armv8mbl.h.

◆ EXC_RETURN_ES [2/5]

#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

Definition at line 2002 of file core_armv8mml.h.

◆ EXC_RETURN_ES [3/5]

#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

Definition at line 1302 of file core_cm23.h.

◆ EXC_RETURN_ES [4/5]

#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

Definition at line 2077 of file core_cm33.h.

◆ EXC_RETURN_ES [5/5]

#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */

Definition at line 2077 of file core_cm35p.h.

◆ EXC_RETURN_FTYPE [1/5]

#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

Definition at line 1224 of file core_armv8mbl.h.

◆ EXC_RETURN_FTYPE [2/5]

#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

Definition at line 1999 of file core_armv8mml.h.

◆ EXC_RETURN_FTYPE [3/5]

#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

Definition at line 1299 of file core_cm23.h.

◆ EXC_RETURN_FTYPE [4/5]

#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

Definition at line 2074 of file core_cm33.h.

◆ EXC_RETURN_FTYPE [5/5]

#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */

Definition at line 2074 of file core_cm35p.h.

◆ EXC_RETURN_HANDLER [1/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 603 of file core_cm0.h.

◆ EXC_RETURN_HANDLER [2/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 721 of file core_cm0plus.h.

◆ EXC_RETURN_HANDLER [3/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 630 of file core_cm1.h.

◆ EXC_RETURN_HANDLER [4/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 1458 of file core_cm3.h.

◆ EXC_RETURN_HANDLER [5/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 1631 of file core_cm4.h.

◆ EXC_RETURN_HANDLER [6/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 1854 of file core_cm7.h.

◆ EXC_RETURN_HANDLER [7/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 731 of file core_sc000.h.

◆ EXC_RETURN_HANDLER [8/8]

#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */

Definition at line 1441 of file core_sc300.h.

◆ EXC_RETURN_HANDLER_FPU [1/2]

#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */

Definition at line 1634 of file core_cm4.h.

◆ EXC_RETURN_HANDLER_FPU [2/2]

#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */

Definition at line 1857 of file core_cm7.h.

◆ EXC_RETURN_MODE [1/5]

#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

Definition at line 1225 of file core_armv8mbl.h.

◆ EXC_RETURN_MODE [2/5]

#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

Definition at line 2000 of file core_armv8mml.h.

◆ EXC_RETURN_MODE [3/5]

#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

Definition at line 1300 of file core_cm23.h.

◆ EXC_RETURN_MODE [4/5]

#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

Definition at line 2075 of file core_cm33.h.

◆ EXC_RETURN_MODE [5/5]

#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */

Definition at line 2075 of file core_cm35p.h.

◆ EXC_RETURN_PREFIX [1/5]

#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

Definition at line 1221 of file core_armv8mbl.h.

◆ EXC_RETURN_PREFIX [2/5]

#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

Definition at line 1996 of file core_armv8mml.h.

◆ EXC_RETURN_PREFIX [3/5]

#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

Definition at line 1296 of file core_cm23.h.

◆ EXC_RETURN_PREFIX [4/5]

#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

Definition at line 2071 of file core_cm33.h.

◆ EXC_RETURN_PREFIX [5/5]

#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */

Definition at line 2071 of file core_cm35p.h.

◆ EXC_RETURN_S [1/5]

#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

Definition at line 1222 of file core_armv8mbl.h.

◆ EXC_RETURN_S [2/5]

#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

Definition at line 1997 of file core_armv8mml.h.

◆ EXC_RETURN_S [3/5]

#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

Definition at line 1297 of file core_cm23.h.

◆ EXC_RETURN_S [4/5]

#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

Definition at line 2072 of file core_cm33.h.

◆ EXC_RETURN_S [5/5]

#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */

Definition at line 2072 of file core_cm35p.h.

◆ EXC_RETURN_SPSEL [1/5]

#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

Definition at line 1226 of file core_armv8mbl.h.

◆ EXC_RETURN_SPSEL [2/5]

#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

Definition at line 2001 of file core_armv8mml.h.

◆ EXC_RETURN_SPSEL [3/5]

#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

Definition at line 1301 of file core_cm23.h.

◆ EXC_RETURN_SPSEL [4/5]

#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

Definition at line 2076 of file core_cm33.h.

◆ EXC_RETURN_SPSEL [5/5]

#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */

Definition at line 2076 of file core_cm35p.h.

◆ EXC_RETURN_THREAD_MSP [1/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 604 of file core_cm0.h.

◆ EXC_RETURN_THREAD_MSP [2/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 722 of file core_cm0plus.h.

◆ EXC_RETURN_THREAD_MSP [3/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 631 of file core_cm1.h.

◆ EXC_RETURN_THREAD_MSP [4/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 1459 of file core_cm3.h.

◆ EXC_RETURN_THREAD_MSP [5/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 1632 of file core_cm4.h.

◆ EXC_RETURN_THREAD_MSP [6/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 1855 of file core_cm7.h.

◆ EXC_RETURN_THREAD_MSP [7/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 732 of file core_sc000.h.

◆ EXC_RETURN_THREAD_MSP [8/8]

#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */

Definition at line 1442 of file core_sc300.h.

◆ EXC_RETURN_THREAD_MSP_FPU [1/2]

#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */

Definition at line 1635 of file core_cm4.h.

◆ EXC_RETURN_THREAD_MSP_FPU [2/2]

#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */

Definition at line 1858 of file core_cm7.h.

◆ EXC_RETURN_THREAD_PSP [1/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 605 of file core_cm0.h.

◆ EXC_RETURN_THREAD_PSP [2/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 723 of file core_cm0plus.h.

◆ EXC_RETURN_THREAD_PSP [3/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 632 of file core_cm1.h.

◆ EXC_RETURN_THREAD_PSP [4/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 1460 of file core_cm3.h.

◆ EXC_RETURN_THREAD_PSP [5/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 1633 of file core_cm4.h.

◆ EXC_RETURN_THREAD_PSP [6/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 1856 of file core_cm7.h.

◆ EXC_RETURN_THREAD_PSP [7/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 733 of file core_sc000.h.

◆ EXC_RETURN_THREAD_PSP [8/8]

#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */

Definition at line 1443 of file core_sc300.h.

◆ EXC_RETURN_THREAD_PSP_FPU [1/2]

#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */

Definition at line 1636 of file core_cm4.h.

◆ EXC_RETURN_THREAD_PSP_FPU [2/2]

#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */

Definition at line 1859 of file core_cm7.h.

◆ FNC_RETURN [1/5]

#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

Definition at line 1218 of file core_armv8mbl.h.

◆ FNC_RETURN [2/5]

#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

Definition at line 1993 of file core_armv8mml.h.

◆ FNC_RETURN [3/5]

#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

Definition at line 1293 of file core_cm23.h.

◆ FNC_RETURN [4/5]

#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

Definition at line 2068 of file core_cm33.h.

◆ FNC_RETURN [5/5]

#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */

Definition at line 2068 of file core_cm35p.h.

◆ FPU [1/6]

#define FPU ((FPU_Type *) FPU_BASE )

Floating Point Unit

Definition at line 2063 of file core_armv81mml.h.

◆ FPU [2/6]

#define FPU ((FPU_Type *) FPU_BASE )

Floating Point Unit

Definition at line 1907 of file core_armv8mml.h.

◆ FPU [3/6]

#define FPU ((FPU_Type *) FPU_BASE )

Floating Point Unit

Definition at line 1982 of file core_cm33.h.

◆ FPU [4/6]

#define FPU ((FPU_Type *) FPU_BASE )

Floating Point Unit

Definition at line 1982 of file core_cm35p.h.

◆ FPU [5/6]

#define FPU ((FPU_Type *) FPU_BASE )

Floating Point Unit

Definition at line 1569 of file core_cm4.h.

◆ FPU [6/6]

#define FPU ((FPU_Type *) FPU_BASE )

Floating Point Unit

Definition at line 1792 of file core_cm7.h.

◆ FPU_BASE [1/6]

#define FPU_BASE (SCS_BASE + 0x0F30UL)

Floating Point Unit

Definition at line 2062 of file core_armv81mml.h.

◆ FPU_BASE [2/6]

#define FPU_BASE (SCS_BASE + 0x0F30UL)

Floating Point Unit

Definition at line 1906 of file core_armv8mml.h.

◆ FPU_BASE [3/6]

#define FPU_BASE (SCS_BASE + 0x0F30UL)

Floating Point Unit

Definition at line 1981 of file core_cm33.h.

◆ FPU_BASE [4/6]

#define FPU_BASE (SCS_BASE + 0x0F30UL)

Floating Point Unit

Definition at line 1981 of file core_cm35p.h.

◆ FPU_BASE [5/6]

#define FPU_BASE (SCS_BASE + 0x0F30UL)

Floating Point Unit

Definition at line 1568 of file core_cm4.h.

◆ FPU_BASE [6/6]

#define FPU_BASE (SCS_BASE + 0x0F30UL)

Floating Point Unit

Definition at line 1791 of file core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Msk [1/6]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1810 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [2/6]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1654 of file core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Msk [3/6]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1729 of file core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Msk [4/6]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1729 of file core_cm35p.h.

◆ FPU_FPCAR_ADDRESS_Msk [5/6]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1345 of file core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Msk [6/6]

#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)

FPCAR: ADDRESS bit Mask

Definition at line 1568 of file core_cm7.h.

◆ FPU_FPCAR_ADDRESS_Pos [1/6]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1809 of file core_armv81mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [2/6]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1653 of file core_armv8mml.h.

◆ FPU_FPCAR_ADDRESS_Pos [3/6]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1728 of file core_cm33.h.

◆ FPU_FPCAR_ADDRESS_Pos [4/6]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1728 of file core_cm35p.h.

◆ FPU_FPCAR_ADDRESS_Pos [5/6]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1344 of file core_cm4.h.

◆ FPU_FPCAR_ADDRESS_Pos [6/6]

#define FPU_FPCAR_ADDRESS_Pos 3U

FPCAR: ADDRESS bit Position

Definition at line 1567 of file core_cm7.h.

◆ FPU_FPCCR_ASPEN_Msk [1/6]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1758 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Msk [2/6]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1602 of file core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Msk [3/6]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1677 of file core_cm33.h.

◆ FPU_FPCCR_ASPEN_Msk [4/6]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1677 of file core_cm35p.h.

◆ FPU_FPCCR_ASPEN_Msk [5/6]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1317 of file core_cm4.h.

◆ FPU_FPCCR_ASPEN_Msk [6/6]

#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)

FPCCR: ASPEN bit Mask

Definition at line 1540 of file core_cm7.h.

◆ FPU_FPCCR_ASPEN_Pos [1/6]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1757 of file core_armv81mml.h.

◆ FPU_FPCCR_ASPEN_Pos [2/6]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1601 of file core_armv8mml.h.

◆ FPU_FPCCR_ASPEN_Pos [3/6]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1676 of file core_cm33.h.

◆ FPU_FPCCR_ASPEN_Pos [4/6]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1676 of file core_cm35p.h.

◆ FPU_FPCCR_ASPEN_Pos [5/6]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1316 of file core_cm4.h.

◆ FPU_FPCCR_ASPEN_Pos [6/6]

#define FPU_FPCCR_ASPEN_Pos 31U

FPCCR: ASPEN bit Position

Definition at line 1539 of file core_cm7.h.

◆ FPU_FPCCR_BFRDY_Msk [1/6]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1788 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Msk [2/6]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1632 of file core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Msk [3/6]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1707 of file core_cm33.h.

◆ FPU_FPCCR_BFRDY_Msk [4/6]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1707 of file core_cm35p.h.

◆ FPU_FPCCR_BFRDY_Msk [5/6]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1326 of file core_cm4.h.

◆ FPU_FPCCR_BFRDY_Msk [6/6]

#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)

FPCCR: BFRDY bit Mask

Definition at line 1549 of file core_cm7.h.

◆ FPU_FPCCR_BFRDY_Pos [1/6]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1787 of file core_armv81mml.h.

◆ FPU_FPCCR_BFRDY_Pos [2/6]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1631 of file core_armv8mml.h.

◆ FPU_FPCCR_BFRDY_Pos [3/6]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1706 of file core_cm33.h.

◆ FPU_FPCCR_BFRDY_Pos [4/6]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1706 of file core_cm35p.h.

◆ FPU_FPCCR_BFRDY_Pos [5/6]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1325 of file core_cm4.h.

◆ FPU_FPCCR_BFRDY_Pos [6/6]

#define FPU_FPCCR_BFRDY_Pos 6U

FPCCR: BFRDY Position

Definition at line 1548 of file core_cm7.h.

◆ FPU_FPCCR_CLRONRET_Msk [1/4]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1767 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [2/4]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1611 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Msk [3/4]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1686 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Msk [4/4]

#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)

FPCCR: CLRONRET bit Mask

Definition at line 1686 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRET_Pos [1/4]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1766 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [2/4]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1610 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRET_Pos [3/4]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1685 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRET_Pos [4/4]

#define FPU_FPCCR_CLRONRET_Pos 28U

FPCCR: CLRONRET Position

Definition at line 1685 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRETS_Msk [1/4]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1770 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [2/4]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1614 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Msk [3/4]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1689 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Msk [4/4]

#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)

FPCCR: CLRONRETS bit Mask

Definition at line 1689 of file core_cm35p.h.

◆ FPU_FPCCR_CLRONRETS_Pos [1/4]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1769 of file core_armv81mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [2/4]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1613 of file core_armv8mml.h.

◆ FPU_FPCCR_CLRONRETS_Pos [3/4]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1688 of file core_cm33.h.

◆ FPU_FPCCR_CLRONRETS_Pos [4/4]

#define FPU_FPCCR_CLRONRETS_Pos 27U

FPCCR: CLRONRETS Position

Definition at line 1688 of file core_cm35p.h.

◆ FPU_FPCCR_HFRDY_Msk [1/6]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1794 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Msk [2/6]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1638 of file core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Msk [3/6]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1713 of file core_cm33.h.

◆ FPU_FPCCR_HFRDY_Msk [4/6]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1713 of file core_cm35p.h.

◆ FPU_FPCCR_HFRDY_Msk [5/6]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1332 of file core_cm4.h.

◆ FPU_FPCCR_HFRDY_Msk [6/6]

#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)

FPCCR: HFRDY bit Mask

Definition at line 1555 of file core_cm7.h.

◆ FPU_FPCCR_HFRDY_Pos [1/6]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1793 of file core_armv81mml.h.

◆ FPU_FPCCR_HFRDY_Pos [2/6]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1637 of file core_armv8mml.h.

◆ FPU_FPCCR_HFRDY_Pos [3/6]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1712 of file core_cm33.h.

◆ FPU_FPCCR_HFRDY_Pos [4/6]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1712 of file core_cm35p.h.

◆ FPU_FPCCR_HFRDY_Pos [5/6]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1331 of file core_cm4.h.

◆ FPU_FPCCR_HFRDY_Pos [6/6]

#define FPU_FPCCR_HFRDY_Pos 4U

FPCCR: HFRDY Position

Definition at line 1554 of file core_cm7.h.

◆ FPU_FPCCR_LSPACT_Msk [1/6]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1806 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Msk [2/6]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1650 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Msk [3/6]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1725 of file core_cm33.h.

◆ FPU_FPCCR_LSPACT_Msk [4/6]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1725 of file core_cm35p.h.

◆ FPU_FPCCR_LSPACT_Msk [5/6]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1341 of file core_cm4.h.

◆ FPU_FPCCR_LSPACT_Msk [6/6]

#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)

FPCCR: Lazy state preservation active bit Mask

Definition at line 1564 of file core_cm7.h.

◆ FPU_FPCCR_LSPACT_Pos [1/6]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1805 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPACT_Pos [2/6]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1649 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPACT_Pos [3/6]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1724 of file core_cm33.h.

◆ FPU_FPCCR_LSPACT_Pos [4/6]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1724 of file core_cm35p.h.

◆ FPU_FPCCR_LSPACT_Pos [5/6]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1340 of file core_cm4.h.

◆ FPU_FPCCR_LSPACT_Pos [6/6]

#define FPU_FPCCR_LSPACT_Pos 0U

FPCCR: Lazy state preservation active bit Position

Definition at line 1563 of file core_cm7.h.

◆ FPU_FPCCR_LSPEN_Msk [1/6]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1761 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Msk [2/6]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1605 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Msk [3/6]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1680 of file core_cm33.h.

◆ FPU_FPCCR_LSPEN_Msk [4/6]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1680 of file core_cm35p.h.

◆ FPU_FPCCR_LSPEN_Msk [5/6]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1320 of file core_cm4.h.

◆ FPU_FPCCR_LSPEN_Msk [6/6]

#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)

FPCCR: LSPEN bit Mask

Definition at line 1543 of file core_cm7.h.

◆ FPU_FPCCR_LSPEN_Pos [1/6]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1760 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPEN_Pos [2/6]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1604 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPEN_Pos [3/6]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1679 of file core_cm33.h.

◆ FPU_FPCCR_LSPEN_Pos [4/6]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1679 of file core_cm35p.h.

◆ FPU_FPCCR_LSPEN_Pos [5/6]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1319 of file core_cm4.h.

◆ FPU_FPCCR_LSPEN_Pos [6/6]

#define FPU_FPCCR_LSPEN_Pos 30U

FPCCR: LSPEN Position

Definition at line 1542 of file core_cm7.h.

◆ FPU_FPCCR_LSPENS_Msk [1/4]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1764 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Msk [2/4]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1608 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Msk [3/4]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1683 of file core_cm33.h.

◆ FPU_FPCCR_LSPENS_Msk [4/4]

#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)

FPCCR: LSPENS bit Mask

Definition at line 1683 of file core_cm35p.h.

◆ FPU_FPCCR_LSPENS_Pos [1/4]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1763 of file core_armv81mml.h.

◆ FPU_FPCCR_LSPENS_Pos [2/4]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1607 of file core_armv8mml.h.

◆ FPU_FPCCR_LSPENS_Pos [3/4]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1682 of file core_cm33.h.

◆ FPU_FPCCR_LSPENS_Pos [4/4]

#define FPU_FPCCR_LSPENS_Pos 29U

FPCCR: LSPENS Position

Definition at line 1682 of file core_cm35p.h.

◆ FPU_FPCCR_MMRDY_Msk [1/6]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1791 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Msk [2/6]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1635 of file core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Msk [3/6]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1710 of file core_cm33.h.

◆ FPU_FPCCR_MMRDY_Msk [4/6]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1710 of file core_cm35p.h.

◆ FPU_FPCCR_MMRDY_Msk [5/6]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1329 of file core_cm4.h.

◆ FPU_FPCCR_MMRDY_Msk [6/6]

#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)

FPCCR: MMRDY bit Mask

Definition at line 1552 of file core_cm7.h.

◆ FPU_FPCCR_MMRDY_Pos [1/6]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1790 of file core_armv81mml.h.

◆ FPU_FPCCR_MMRDY_Pos [2/6]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1634 of file core_armv8mml.h.

◆ FPU_FPCCR_MMRDY_Pos [3/6]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1709 of file core_cm33.h.

◆ FPU_FPCCR_MMRDY_Pos [4/6]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1709 of file core_cm35p.h.

◆ FPU_FPCCR_MMRDY_Pos [5/6]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1328 of file core_cm4.h.

◆ FPU_FPCCR_MMRDY_Pos [6/6]

#define FPU_FPCCR_MMRDY_Pos 5U

FPCCR: MMRDY Position

Definition at line 1551 of file core_cm7.h.

◆ FPU_FPCCR_MONRDY_Msk [1/6]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1782 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Msk [2/6]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1626 of file core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Msk [3/6]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1701 of file core_cm33.h.

◆ FPU_FPCCR_MONRDY_Msk [4/6]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1701 of file core_cm35p.h.

◆ FPU_FPCCR_MONRDY_Msk [5/6]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1323 of file core_cm4.h.

◆ FPU_FPCCR_MONRDY_Msk [6/6]

#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)

FPCCR: MONRDY bit Mask

Definition at line 1546 of file core_cm7.h.

◆ FPU_FPCCR_MONRDY_Pos [1/6]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1781 of file core_armv81mml.h.

◆ FPU_FPCCR_MONRDY_Pos [2/6]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1625 of file core_armv8mml.h.

◆ FPU_FPCCR_MONRDY_Pos [3/6]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1700 of file core_cm33.h.

◆ FPU_FPCCR_MONRDY_Pos [4/6]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1700 of file core_cm35p.h.

◆ FPU_FPCCR_MONRDY_Pos [5/6]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1322 of file core_cm4.h.

◆ FPU_FPCCR_MONRDY_Pos [6/6]

#define FPU_FPCCR_MONRDY_Pos 8U

FPCCR: MONRDY Position

Definition at line 1545 of file core_cm7.h.

◆ FPU_FPCCR_S_Msk [1/4]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1800 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Msk [2/4]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1644 of file core_armv8mml.h.

◆ FPU_FPCCR_S_Msk [3/4]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1719 of file core_cm33.h.

◆ FPU_FPCCR_S_Msk [4/4]

#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)

FPCCR: Security status of the FP context bit Mask

Definition at line 1719 of file core_cm35p.h.

◆ FPU_FPCCR_S_Pos [1/4]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1799 of file core_armv81mml.h.

◆ FPU_FPCCR_S_Pos [2/4]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1643 of file core_armv8mml.h.

◆ FPU_FPCCR_S_Pos [3/4]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1718 of file core_cm33.h.

◆ FPU_FPCCR_S_Pos [4/4]

#define FPU_FPCCR_S_Pos 2U

FPCCR: Security status of the FP context bit Position

Definition at line 1718 of file core_cm35p.h.

◆ FPU_FPCCR_SFRDY_Msk [1/4]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1785 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Msk [2/4]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1629 of file core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Msk [3/4]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1704 of file core_cm33.h.

◆ FPU_FPCCR_SFRDY_Msk [4/4]

#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)

FPCCR: SFRDY bit Mask

Definition at line 1704 of file core_cm35p.h.

◆ FPU_FPCCR_SFRDY_Pos [1/4]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1784 of file core_armv81mml.h.

◆ FPU_FPCCR_SFRDY_Pos [2/4]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1628 of file core_armv8mml.h.

◆ FPU_FPCCR_SFRDY_Pos [3/4]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1703 of file core_cm33.h.

◆ FPU_FPCCR_SFRDY_Pos [4/4]

#define FPU_FPCCR_SFRDY_Pos 7U

FPCCR: SFRDY Position

Definition at line 1703 of file core_cm35p.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [1/4]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1779 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [2/4]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1623 of file core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [3/4]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1698 of file core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Msk [4/4]

#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)

FPCCR: SPLIMVIOL bit Mask

Definition at line 1698 of file core_cm35p.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [1/4]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1778 of file core_armv81mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [2/4]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1622 of file core_armv8mml.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [3/4]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1697 of file core_cm33.h.

◆ FPU_FPCCR_SPLIMVIOL_Pos [4/4]

#define FPU_FPCCR_SPLIMVIOL_Pos 9U

FPCCR: SPLIMVIOL Position

Definition at line 1697 of file core_cm35p.h.

◆ FPU_FPCCR_THREAD_Msk [1/6]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1797 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Msk [2/6]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1641 of file core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Msk [3/6]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1716 of file core_cm33.h.

◆ FPU_FPCCR_THREAD_Msk [4/6]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1716 of file core_cm35p.h.

◆ FPU_FPCCR_THREAD_Msk [5/6]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1335 of file core_cm4.h.

◆ FPU_FPCCR_THREAD_Msk [6/6]

#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)

FPCCR: processor mode active bit Mask

Definition at line 1558 of file core_cm7.h.

◆ FPU_FPCCR_THREAD_Pos [1/6]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1796 of file core_armv81mml.h.

◆ FPU_FPCCR_THREAD_Pos [2/6]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1640 of file core_armv8mml.h.

◆ FPU_FPCCR_THREAD_Pos [3/6]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1715 of file core_cm33.h.

◆ FPU_FPCCR_THREAD_Pos [4/6]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1715 of file core_cm35p.h.

◆ FPU_FPCCR_THREAD_Pos [5/6]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1334 of file core_cm4.h.

◆ FPU_FPCCR_THREAD_Pos [6/6]

#define FPU_FPCCR_THREAD_Pos 3U

FPCCR: processor mode bit Position

Definition at line 1557 of file core_cm7.h.

◆ FPU_FPCCR_TS_Msk [1/4]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1773 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Msk [2/4]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1617 of file core_armv8mml.h.

◆ FPU_FPCCR_TS_Msk [3/4]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1692 of file core_cm33.h.

◆ FPU_FPCCR_TS_Msk [4/4]

#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)

FPCCR: TS bit Mask

Definition at line 1692 of file core_cm35p.h.

◆ FPU_FPCCR_TS_Pos [1/4]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1772 of file core_armv81mml.h.

◆ FPU_FPCCR_TS_Pos [2/4]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1616 of file core_armv8mml.h.

◆ FPU_FPCCR_TS_Pos [3/4]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1691 of file core_cm33.h.

◆ FPU_FPCCR_TS_Pos [4/4]

#define FPU_FPCCR_TS_Pos 26U

FPCCR: TS Position

Definition at line 1691 of file core_cm35p.h.

◆ FPU_FPCCR_UFRDY_Msk [1/4]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1776 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Msk [2/4]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1620 of file core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Msk [3/4]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1695 of file core_cm33.h.

◆ FPU_FPCCR_UFRDY_Msk [4/4]

#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)

FPCCR: UFRDY bit Mask

Definition at line 1695 of file core_cm35p.h.

◆ FPU_FPCCR_UFRDY_Pos [1/4]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1775 of file core_armv81mml.h.

◆ FPU_FPCCR_UFRDY_Pos [2/4]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1619 of file core_armv8mml.h.

◆ FPU_FPCCR_UFRDY_Pos [3/4]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1694 of file core_cm33.h.

◆ FPU_FPCCR_UFRDY_Pos [4/4]

#define FPU_FPCCR_UFRDY_Pos 10U

FPCCR: UFRDY Position

Definition at line 1694 of file core_cm35p.h.

◆ FPU_FPCCR_USER_Msk [1/6]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1803 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Msk [2/6]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1647 of file core_armv8mml.h.

◆ FPU_FPCCR_USER_Msk [3/6]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1722 of file core_cm33.h.

◆ FPU_FPCCR_USER_Msk [4/6]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1722 of file core_cm35p.h.

◆ FPU_FPCCR_USER_Msk [5/6]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1338 of file core_cm4.h.

◆ FPU_FPCCR_USER_Msk [6/6]

#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)

FPCCR: privilege level bit Mask

Definition at line 1561 of file core_cm7.h.

◆ FPU_FPCCR_USER_Pos [1/6]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1802 of file core_armv81mml.h.

◆ FPU_FPCCR_USER_Pos [2/6]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1646 of file core_armv8mml.h.

◆ FPU_FPCCR_USER_Pos [3/6]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1721 of file core_cm33.h.

◆ FPU_FPCCR_USER_Pos [4/6]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1721 of file core_cm35p.h.

◆ FPU_FPCCR_USER_Pos [5/6]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1337 of file core_cm4.h.

◆ FPU_FPCCR_USER_Pos [6/6]

#define FPU_FPCCR_USER_Pos 1U

FPCCR: privilege level bit Position

Definition at line 1560 of file core_cm7.h.

◆ FPU_FPDSCR_AHP_Msk [1/6]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1814 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Msk [2/6]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1658 of file core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Msk [3/6]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1733 of file core_cm33.h.

◆ FPU_FPDSCR_AHP_Msk [4/6]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1733 of file core_cm35p.h.

◆ FPU_FPDSCR_AHP_Msk [5/6]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1349 of file core_cm4.h.

◆ FPU_FPDSCR_AHP_Msk [6/6]

#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)

FPDSCR: AHP bit Mask

Definition at line 1572 of file core_cm7.h.

◆ FPU_FPDSCR_AHP_Pos [1/6]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1813 of file core_armv81mml.h.

◆ FPU_FPDSCR_AHP_Pos [2/6]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1657 of file core_armv8mml.h.

◆ FPU_FPDSCR_AHP_Pos [3/6]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1732 of file core_cm33.h.

◆ FPU_FPDSCR_AHP_Pos [4/6]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1732 of file core_cm35p.h.

◆ FPU_FPDSCR_AHP_Pos [5/6]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1348 of file core_cm4.h.

◆ FPU_FPDSCR_AHP_Pos [6/6]

#define FPU_FPDSCR_AHP_Pos 26U

FPDSCR: AHP bit Position

Definition at line 1571 of file core_cm7.h.

◆ FPU_FPDSCR_DN_Msk [1/6]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1817 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Msk [2/6]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1661 of file core_armv8mml.h.

◆ FPU_FPDSCR_DN_Msk [3/6]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1736 of file core_cm33.h.

◆ FPU_FPDSCR_DN_Msk [4/6]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1736 of file core_cm35p.h.

◆ FPU_FPDSCR_DN_Msk [5/6]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1352 of file core_cm4.h.

◆ FPU_FPDSCR_DN_Msk [6/6]

#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)

FPDSCR: DN bit Mask

Definition at line 1575 of file core_cm7.h.

◆ FPU_FPDSCR_DN_Pos [1/6]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1816 of file core_armv81mml.h.

◆ FPU_FPDSCR_DN_Pos [2/6]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1660 of file core_armv8mml.h.

◆ FPU_FPDSCR_DN_Pos [3/6]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1735 of file core_cm33.h.

◆ FPU_FPDSCR_DN_Pos [4/6]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1735 of file core_cm35p.h.

◆ FPU_FPDSCR_DN_Pos [5/6]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1351 of file core_cm4.h.

◆ FPU_FPDSCR_DN_Pos [6/6]

#define FPU_FPDSCR_DN_Pos 25U

FPDSCR: DN bit Position

Definition at line 1574 of file core_cm7.h.

◆ FPU_FPDSCR_FZ_Msk [1/6]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1820 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Msk [2/6]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1664 of file core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Msk [3/6]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1739 of file core_cm33.h.

◆ FPU_FPDSCR_FZ_Msk [4/6]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1739 of file core_cm35p.h.

◆ FPU_FPDSCR_FZ_Msk [5/6]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1355 of file core_cm4.h.

◆ FPU_FPDSCR_FZ_Msk [6/6]

#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)

FPDSCR: FZ bit Mask

Definition at line 1578 of file core_cm7.h.

◆ FPU_FPDSCR_FZ_Pos [1/6]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1819 of file core_armv81mml.h.

◆ FPU_FPDSCR_FZ_Pos [2/6]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1663 of file core_armv8mml.h.

◆ FPU_FPDSCR_FZ_Pos [3/6]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1738 of file core_cm33.h.

◆ FPU_FPDSCR_FZ_Pos [4/6]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1738 of file core_cm35p.h.

◆ FPU_FPDSCR_FZ_Pos [5/6]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1354 of file core_cm4.h.

◆ FPU_FPDSCR_FZ_Pos [6/6]

#define FPU_FPDSCR_FZ_Pos 24U

FPDSCR: FZ bit Position

Definition at line 1577 of file core_cm7.h.

◆ FPU_FPDSCR_RMode_Msk [1/6]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1823 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Msk [2/6]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1667 of file core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Msk [3/6]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1742 of file core_cm33.h.

◆ FPU_FPDSCR_RMode_Msk [4/6]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1742 of file core_cm35p.h.

◆ FPU_FPDSCR_RMode_Msk [5/6]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1358 of file core_cm4.h.

◆ FPU_FPDSCR_RMode_Msk [6/6]

#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)

FPDSCR: RMode bit Mask

Definition at line 1581 of file core_cm7.h.

◆ FPU_FPDSCR_RMode_Pos [1/6]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1822 of file core_armv81mml.h.

◆ FPU_FPDSCR_RMode_Pos [2/6]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1666 of file core_armv8mml.h.

◆ FPU_FPDSCR_RMode_Pos [3/6]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1741 of file core_cm33.h.

◆ FPU_FPDSCR_RMode_Pos [4/6]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1741 of file core_cm35p.h.

◆ FPU_FPDSCR_RMode_Pos [5/6]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1357 of file core_cm4.h.

◆ FPU_FPDSCR_RMode_Pos [6/6]

#define FPU_FPDSCR_RMode_Pos 22U

FPDSCR: RMode bit Position

Definition at line 1580 of file core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [1/6]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1848 of file core_armv81mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [2/6]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1692 of file core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [3/6]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1767 of file core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [4/6]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1767 of file core_cm35p.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [5/6]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1383 of file core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Msk [6/6]

#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)

MVFR0: A_SIMD registers bits Mask

Definition at line 1606 of file core_cm7.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [1/6]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1847 of file core_armv81mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [2/6]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1691 of file core_armv8mml.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [3/6]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1766 of file core_cm33.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [4/6]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1766 of file core_cm35p.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [5/6]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1382 of file core_cm4.h.

◆ FPU_MVFR0_A_SIMD_registers_Pos [6/6]

#define FPU_MVFR0_A_SIMD_registers_Pos 0U

MVFR0: A_SIMD registers bits Position

Definition at line 1605 of file core_cm7.h.

◆ FPU_MVFR0_Divide_Msk [1/6]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1836 of file core_armv81mml.h.

◆ FPU_MVFR0_Divide_Msk [2/6]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1680 of file core_armv8mml.h.

◆ FPU_MVFR0_Divide_Msk [3/6]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1755 of file core_cm33.h.

◆ FPU_MVFR0_Divide_Msk [4/6]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1755 of file core_cm35p.h.

◆ FPU_MVFR0_Divide_Msk [5/6]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1371 of file core_cm4.h.

◆ FPU_MVFR0_Divide_Msk [6/6]

#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)

MVFR0: Divide bits Mask

Definition at line 1594 of file core_cm7.h.

◆ FPU_MVFR0_Divide_Pos [1/6]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1835 of file core_armv81mml.h.

◆ FPU_MVFR0_Divide_Pos [2/6]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1679 of file core_armv8mml.h.

◆ FPU_MVFR0_Divide_Pos [3/6]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1754 of file core_cm33.h.

◆ FPU_MVFR0_Divide_Pos [4/6]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1754 of file core_cm35p.h.

◆ FPU_MVFR0_Divide_Pos [5/6]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1370 of file core_cm4.h.

◆ FPU_MVFR0_Divide_Pos [6/6]

#define FPU_MVFR0_Divide_Pos 16U

MVFR0: Divide bits Position

Definition at line 1593 of file core_cm7.h.

◆ FPU_MVFR0_Double_precision_Msk [1/6]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1842 of file core_armv81mml.h.

◆ FPU_MVFR0_Double_precision_Msk [2/6]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1686 of file core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Msk [3/6]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1761 of file core_cm33.h.

◆ FPU_MVFR0_Double_precision_Msk [4/6]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1761 of file core_cm35p.h.

◆ FPU_MVFR0_Double_precision_Msk [5/6]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1377 of file core_cm4.h.

◆ FPU_MVFR0_Double_precision_Msk [6/6]

#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)

MVFR0: Double-precision bits Mask

Definition at line 1600 of file core_cm7.h.

◆ FPU_MVFR0_Double_precision_Pos [1/6]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1841 of file core_armv81mml.h.

◆ FPU_MVFR0_Double_precision_Pos [2/6]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1685 of file core_armv8mml.h.

◆ FPU_MVFR0_Double_precision_Pos [3/6]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1760 of file core_cm33.h.

◆ FPU_MVFR0_Double_precision_Pos [4/6]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1760 of file core_cm35p.h.

◆ FPU_MVFR0_Double_precision_Pos [5/6]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1376 of file core_cm4.h.

◆ FPU_MVFR0_Double_precision_Pos [6/6]

#define FPU_MVFR0_Double_precision_Pos 8U

MVFR0: Double-precision bits Position

Definition at line 1599 of file core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [1/6]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1839 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [2/6]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1683 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [3/6]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1758 of file core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [4/6]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1758 of file core_cm35p.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [5/6]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1374 of file core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Msk [6/6]

#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)

MVFR0: FP exception trapping bits Mask

Definition at line 1597 of file core_cm7.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [1/6]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1838 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [2/6]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1682 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [3/6]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1757 of file core_cm33.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [4/6]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1757 of file core_cm35p.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [5/6]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1373 of file core_cm4.h.

◆ FPU_MVFR0_FP_excep_trapping_Pos [6/6]

#define FPU_MVFR0_FP_excep_trapping_Pos 12U

MVFR0: FP exception trapping bits Position

Definition at line 1596 of file core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [1/6]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1827 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [2/6]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1671 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [3/6]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1746 of file core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [4/6]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1746 of file core_cm35p.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [5/6]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1362 of file core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Msk [6/6]

#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)

MVFR0: FP rounding modes bits Mask

Definition at line 1585 of file core_cm7.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [1/6]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1826 of file core_armv81mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [2/6]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1670 of file core_armv8mml.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [3/6]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1745 of file core_cm33.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [4/6]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1745 of file core_cm35p.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [5/6]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1361 of file core_cm4.h.

◆ FPU_MVFR0_FP_rounding_modes_Pos [6/6]

#define FPU_MVFR0_FP_rounding_modes_Pos 28U

MVFR0: FP rounding modes bits Position

Definition at line 1584 of file core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Msk [1/6]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1830 of file core_armv81mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [2/6]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1674 of file core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Msk [3/6]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1749 of file core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Msk [4/6]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1749 of file core_cm35p.h.

◆ FPU_MVFR0_Short_vectors_Msk [5/6]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1365 of file core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Msk [6/6]

#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)

MVFR0: Short vectors bits Mask

Definition at line 1588 of file core_cm7.h.

◆ FPU_MVFR0_Short_vectors_Pos [1/6]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1829 of file core_armv81mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [2/6]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1673 of file core_armv8mml.h.

◆ FPU_MVFR0_Short_vectors_Pos [3/6]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1748 of file core_cm33.h.

◆ FPU_MVFR0_Short_vectors_Pos [4/6]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1748 of file core_cm35p.h.

◆ FPU_MVFR0_Short_vectors_Pos [5/6]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1364 of file core_cm4.h.

◆ FPU_MVFR0_Short_vectors_Pos [6/6]

#define FPU_MVFR0_Short_vectors_Pos 24U

MVFR0: Short vectors bits Position

Definition at line 1587 of file core_cm7.h.

◆ FPU_MVFR0_Single_precision_Msk [1/6]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1845 of file core_armv81mml.h.

◆ FPU_MVFR0_Single_precision_Msk [2/6]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1689 of file core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Msk [3/6]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1764 of file core_cm33.h.

◆ FPU_MVFR0_Single_precision_Msk [4/6]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1764 of file core_cm35p.h.

◆ FPU_MVFR0_Single_precision_Msk [5/6]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1380 of file core_cm4.h.

◆ FPU_MVFR0_Single_precision_Msk [6/6]

#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)

MVFR0: Single-precision bits Mask

Definition at line 1603 of file core_cm7.h.

◆ FPU_MVFR0_Single_precision_Pos [1/6]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1844 of file core_armv81mml.h.

◆ FPU_MVFR0_Single_precision_Pos [2/6]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1688 of file core_armv8mml.h.

◆ FPU_MVFR0_Single_precision_Pos [3/6]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1763 of file core_cm33.h.

◆ FPU_MVFR0_Single_precision_Pos [4/6]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1763 of file core_cm35p.h.

◆ FPU_MVFR0_Single_precision_Pos [5/6]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1379 of file core_cm4.h.

◆ FPU_MVFR0_Single_precision_Pos [6/6]

#define FPU_MVFR0_Single_precision_Pos 4U

MVFR0: Single-precision bits Position

Definition at line 1602 of file core_cm7.h.

◆ FPU_MVFR0_Square_root_Msk [1/6]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1833 of file core_armv81mml.h.

◆ FPU_MVFR0_Square_root_Msk [2/6]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1677 of file core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Msk [3/6]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1752 of file core_cm33.h.

◆ FPU_MVFR0_Square_root_Msk [4/6]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1752 of file core_cm35p.h.

◆ FPU_MVFR0_Square_root_Msk [5/6]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1368 of file core_cm4.h.

◆ FPU_MVFR0_Square_root_Msk [6/6]

#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)

MVFR0: Square root bits Mask

Definition at line 1591 of file core_cm7.h.

◆ FPU_MVFR0_Square_root_Pos [1/6]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1832 of file core_armv81mml.h.

◆ FPU_MVFR0_Square_root_Pos [2/6]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1676 of file core_armv8mml.h.

◆ FPU_MVFR0_Square_root_Pos [3/6]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1751 of file core_cm33.h.

◆ FPU_MVFR0_Square_root_Pos [4/6]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1751 of file core_cm35p.h.

◆ FPU_MVFR0_Square_root_Pos [5/6]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1367 of file core_cm4.h.

◆ FPU_MVFR0_Square_root_Pos [6/6]

#define FPU_MVFR0_Square_root_Pos 20U

MVFR0: Square root bits Position

Definition at line 1590 of file core_cm7.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [1/6]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1858 of file core_armv81mml.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [2/6]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1702 of file core_armv8mml.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [3/6]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1777 of file core_cm33.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [4/6]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1777 of file core_cm35p.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [5/6]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1393 of file core_cm4.h.

◆ FPU_MVFR1_D_NaN_mode_Msk [6/6]

#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)

MVFR1: D_NaN mode bits Mask

Definition at line 1616 of file core_cm7.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [1/6]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1857 of file core_armv81mml.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [2/6]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1701 of file core_armv8mml.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [3/6]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1776 of file core_cm33.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [4/6]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1776 of file core_cm35p.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [5/6]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1392 of file core_cm4.h.

◆ FPU_MVFR1_D_NaN_mode_Pos [6/6]

#define FPU_MVFR1_D_NaN_mode_Pos 4U

MVFR1: D_NaN mode bits Position

Definition at line 1615 of file core_cm7.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [1/6]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1852 of file core_armv81mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [2/6]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1696 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [3/6]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1771 of file core_cm33.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [4/6]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1771 of file core_cm35p.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [5/6]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1387 of file core_cm4.h.

◆ FPU_MVFR1_FP_fused_MAC_Msk [6/6]

#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)

MVFR1: FP fused MAC bits Mask

Definition at line 1610 of file core_cm7.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [1/6]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1851 of file core_armv81mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [2/6]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1695 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [3/6]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1770 of file core_cm33.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [4/6]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1770 of file core_cm35p.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [5/6]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1386 of file core_cm4.h.

◆ FPU_MVFR1_FP_fused_MAC_Pos [6/6]

#define FPU_MVFR1_FP_fused_MAC_Pos 28U

MVFR1: FP fused MAC bits Position

Definition at line 1609 of file core_cm7.h.

◆ FPU_MVFR1_FP_HPFP_Msk [1/6]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1855 of file core_armv81mml.h.

◆ FPU_MVFR1_FP_HPFP_Msk [2/6]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1699 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_HPFP_Msk [3/6]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1774 of file core_cm33.h.

◆ FPU_MVFR1_FP_HPFP_Msk [4/6]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1774 of file core_cm35p.h.

◆ FPU_MVFR1_FP_HPFP_Msk [5/6]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1390 of file core_cm4.h.

◆ FPU_MVFR1_FP_HPFP_Msk [6/6]

#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)

MVFR1: FP HPFP bits Mask

Definition at line 1613 of file core_cm7.h.

◆ FPU_MVFR1_FP_HPFP_Pos [1/6]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1854 of file core_armv81mml.h.

◆ FPU_MVFR1_FP_HPFP_Pos [2/6]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1698 of file core_armv8mml.h.

◆ FPU_MVFR1_FP_HPFP_Pos [3/6]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1773 of file core_cm33.h.

◆ FPU_MVFR1_FP_HPFP_Pos [4/6]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1773 of file core_cm35p.h.

◆ FPU_MVFR1_FP_HPFP_Pos [5/6]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1389 of file core_cm4.h.

◆ FPU_MVFR1_FP_HPFP_Pos [6/6]

#define FPU_MVFR1_FP_HPFP_Pos 24U

MVFR1: FP HPFP bits Position

Definition at line 1612 of file core_cm7.h.

◆ FPU_MVFR1_FtZ_mode_Msk [1/6]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1861 of file core_armv81mml.h.

◆ FPU_MVFR1_FtZ_mode_Msk [2/6]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1705 of file core_armv8mml.h.

◆ FPU_MVFR1_FtZ_mode_Msk [3/6]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1780 of file core_cm33.h.

◆ FPU_MVFR1_FtZ_mode_Msk [4/6]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1780 of file core_cm35p.h.

◆ FPU_MVFR1_FtZ_mode_Msk [5/6]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1396 of file core_cm4.h.

◆ FPU_MVFR1_FtZ_mode_Msk [6/6]

#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)

MVFR1: FtZ mode bits Mask

Definition at line 1619 of file core_cm7.h.

◆ FPU_MVFR1_FtZ_mode_Pos [1/6]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1860 of file core_armv81mml.h.

◆ FPU_MVFR1_FtZ_mode_Pos [2/6]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1704 of file core_armv8mml.h.

◆ FPU_MVFR1_FtZ_mode_Pos [3/6]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1779 of file core_cm33.h.

◆ FPU_MVFR1_FtZ_mode_Pos [4/6]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1779 of file core_cm35p.h.

◆ FPU_MVFR1_FtZ_mode_Pos [5/6]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1395 of file core_cm4.h.

◆ FPU_MVFR1_FtZ_mode_Pos [6/6]

#define FPU_MVFR1_FtZ_mode_Pos 0U

MVFR1: FtZ mode bits Position

Definition at line 1618 of file core_cm7.h.

◆ FPU_MVFR2_VFP_Misc_Msk [1/2]

#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

Definition at line 1401 of file core_cm4.h.

◆ FPU_MVFR2_VFP_Misc_Msk [2/2]

#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos)

MVFR2: VFP Misc bits Mask

Definition at line 1624 of file core_cm7.h.

◆ FPU_MVFR2_VFP_Misc_Pos [1/2]

#define FPU_MVFR2_VFP_Misc_Pos 4U

MVFR2: VFP Misc bits Position

Definition at line 1400 of file core_cm4.h.

◆ FPU_MVFR2_VFP_Misc_Pos [2/2]

#define FPU_MVFR2_VFP_Misc_Pos 4U

MVFR2: VFP Misc bits Position

Definition at line 1623 of file core_cm7.h.

◆ IPSR_ISR_Msk [1/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 366 of file core_armv81mml.h.

◆ IPSR_ISR_Msk [2/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 275 of file core_armv8mbl.h.

◆ IPSR_ISR_Msk [3/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 365 of file core_armv8mml.h.

◆ IPSR_ISR_Msk [4/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 241 of file core_cm0.h.

◆ IPSR_ISR_Msk [5/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 252 of file core_cm0plus.h.

◆ IPSR_ISR_Msk [6/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 241 of file core_cm1.h.

◆ IPSR_ISR_Msk [7/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 275 of file core_cm23.h.

◆ IPSR_ISR_Msk [8/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 252 of file core_cm3.h.

◆ IPSR_ISR_Msk [9/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 365 of file core_cm33.h.

◆ IPSR_ISR_Msk [10/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 365 of file core_cm35p.h.

◆ IPSR_ISR_Msk [11/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 310 of file core_cm4.h.

◆ IPSR_ISR_Msk [12/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 325 of file core_cm7.h.

◆ IPSR_ISR_Msk [13/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 247 of file core_sc000.h.

◆ IPSR_ISR_Msk [14/14]

#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)

IPSR: ISR Mask

Definition at line 252 of file core_sc300.h.

◆ IPSR_ISR_Pos [1/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 365 of file core_armv81mml.h.

◆ IPSR_ISR_Pos [2/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 274 of file core_armv8mbl.h.

◆ IPSR_ISR_Pos [3/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 364 of file core_armv8mml.h.

◆ IPSR_ISR_Pos [4/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 240 of file core_cm0.h.

◆ IPSR_ISR_Pos [5/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 251 of file core_cm0plus.h.

◆ IPSR_ISR_Pos [6/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 240 of file core_cm1.h.

◆ IPSR_ISR_Pos [7/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 274 of file core_cm23.h.

◆ IPSR_ISR_Pos [8/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 251 of file core_cm3.h.

◆ IPSR_ISR_Pos [9/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 364 of file core_cm33.h.

◆ IPSR_ISR_Pos [10/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 364 of file core_cm35p.h.

◆ IPSR_ISR_Pos [11/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 309 of file core_cm4.h.

◆ IPSR_ISR_Pos [12/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 324 of file core_cm7.h.

◆ IPSR_ISR_Pos [13/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 246 of file core_sc000.h.

◆ IPSR_ISR_Pos [14/14]

#define IPSR_ISR_Pos 0U

IPSR: ISR Position

Definition at line 251 of file core_sc300.h.

◆ ITM [1/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 2047 of file core_armv81mml.h.

◆ ITM [2/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 1891 of file core_armv8mml.h.

◆ ITM [3/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 1388 of file core_cm3.h.

◆ ITM [4/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 1966 of file core_cm33.h.

◆ ITM [5/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 1966 of file core_cm35p.h.

◆ ITM [6/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 1558 of file core_cm4.h.

◆ ITM [7/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 1781 of file core_cm7.h.

◆ ITM [8/8]

#define ITM ((ITM_Type *) ITM_BASE )

ITM configuration struct

Definition at line 1371 of file core_sc300.h.

◆ ITM_BASE [1/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 2035 of file core_armv81mml.h.

◆ ITM_BASE [2/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 1879 of file core_armv8mml.h.

◆ ITM_BASE [3/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 1376 of file core_cm3.h.

◆ ITM_BASE [4/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 1954 of file core_cm33.h.

◆ ITM_BASE [5/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 1954 of file core_cm35p.h.

◆ ITM_BASE [6/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 1546 of file core_cm4.h.

◆ ITM_BASE [7/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 1769 of file core_cm7.h.

◆ ITM_BASE [8/8]

#define ITM_BASE (0xE0000000UL)

ITM Base Address

Definition at line 1359 of file core_sc300.h.

◆ ITM_LSR_Access_Msk [1/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1184 of file core_armv81mml.h.

◆ ITM_LSR_Access_Msk [2/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1088 of file core_armv8mml.h.

◆ ITM_LSR_Access_Msk [3/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 823 of file core_cm3.h.

◆ ITM_LSR_Access_Msk [4/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1088 of file core_cm33.h.

◆ ITM_LSR_Access_Msk [5/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1088 of file core_cm35p.h.

◆ ITM_LSR_Access_Msk [6/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 881 of file core_cm4.h.

◆ ITM_LSR_Access_Msk [7/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 1101 of file core_cm7.h.

◆ ITM_LSR_Access_Msk [8/8]

#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)

ITM LSR: Access Mask

Definition at line 808 of file core_sc300.h.

◆ ITM_LSR_Access_Pos [1/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1183 of file core_armv81mml.h.

◆ ITM_LSR_Access_Pos [2/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1087 of file core_armv8mml.h.

◆ ITM_LSR_Access_Pos [3/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 822 of file core_cm3.h.

◆ ITM_LSR_Access_Pos [4/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1087 of file core_cm33.h.

◆ ITM_LSR_Access_Pos [5/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1087 of file core_cm35p.h.

◆ ITM_LSR_Access_Pos [6/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 880 of file core_cm4.h.

◆ ITM_LSR_Access_Pos [7/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 1100 of file core_cm7.h.

◆ ITM_LSR_Access_Pos [8/8]

#define ITM_LSR_Access_Pos 1U

ITM LSR: Access Position

Definition at line 807 of file core_sc300.h.

◆ ITM_LSR_ByteAcc_Msk [1/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1181 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Msk [2/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1085 of file core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Msk [3/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 820 of file core_cm3.h.

◆ ITM_LSR_ByteAcc_Msk [4/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1085 of file core_cm33.h.

◆ ITM_LSR_ByteAcc_Msk [5/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1085 of file core_cm35p.h.

◆ ITM_LSR_ByteAcc_Msk [6/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 878 of file core_cm4.h.

◆ ITM_LSR_ByteAcc_Msk [7/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 1098 of file core_cm7.h.

◆ ITM_LSR_ByteAcc_Msk [8/8]

#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)

ITM LSR: ByteAcc Mask

Definition at line 805 of file core_sc300.h.

◆ ITM_LSR_ByteAcc_Pos [1/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1180 of file core_armv81mml.h.

◆ ITM_LSR_ByteAcc_Pos [2/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1084 of file core_armv8mml.h.

◆ ITM_LSR_ByteAcc_Pos [3/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 819 of file core_cm3.h.

◆ ITM_LSR_ByteAcc_Pos [4/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1084 of file core_cm33.h.

◆ ITM_LSR_ByteAcc_Pos [5/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1084 of file core_cm35p.h.

◆ ITM_LSR_ByteAcc_Pos [6/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 877 of file core_cm4.h.

◆ ITM_LSR_ByteAcc_Pos [7/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 1097 of file core_cm7.h.

◆ ITM_LSR_ByteAcc_Pos [8/8]

#define ITM_LSR_ByteAcc_Pos 2U

ITM LSR: ByteAcc Position

Definition at line 804 of file core_sc300.h.

◆ ITM_LSR_Present_Msk [1/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1187 of file core_armv81mml.h.

◆ ITM_LSR_Present_Msk [2/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1091 of file core_armv8mml.h.

◆ ITM_LSR_Present_Msk [3/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 826 of file core_cm3.h.

◆ ITM_LSR_Present_Msk [4/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1091 of file core_cm33.h.

◆ ITM_LSR_Present_Msk [5/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1091 of file core_cm35p.h.

◆ ITM_LSR_Present_Msk [6/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 884 of file core_cm4.h.

◆ ITM_LSR_Present_Msk [7/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 1104 of file core_cm7.h.

◆ ITM_LSR_Present_Msk [8/8]

#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)

ITM LSR: Present Mask

Definition at line 811 of file core_sc300.h.

◆ ITM_LSR_Present_Pos [1/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1186 of file core_armv81mml.h.

◆ ITM_LSR_Present_Pos [2/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1090 of file core_armv8mml.h.

◆ ITM_LSR_Present_Pos [3/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 825 of file core_cm3.h.

◆ ITM_LSR_Present_Pos [4/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1090 of file core_cm33.h.

◆ ITM_LSR_Present_Pos [5/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1090 of file core_cm35p.h.

◆ ITM_LSR_Present_Pos [6/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 883 of file core_cm4.h.

◆ ITM_LSR_Present_Pos [7/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 1103 of file core_cm7.h.

◆ ITM_LSR_Present_Pos [8/8]

#define ITM_LSR_Present_Pos 0U

ITM LSR: Present Position

Definition at line 810 of file core_sc300.h.

◆ ITM_RXBUFFER_EMPTY [1/7]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2892 of file core_armv81mml.h.

◆ ITM_RXBUFFER_EMPTY [2/7]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2759 of file core_armv8mml.h.

◆ ITM_RXBUFFER_EMPTY [3/7]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 1861 of file core_cm3.h.

◆ ITM_RXBUFFER_EMPTY [4/7]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2834 of file core_cm33.h.

◆ ITM_RXBUFFER_EMPTY [5/7]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2834 of file core_cm35p.h.

◆ ITM_RXBUFFER_EMPTY [6/7]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2048 of file core_cm4.h.

◆ ITM_RXBUFFER_EMPTY [7/7]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2649 of file core_cm7.h.

◆ ITM_STIM_DISABLED_Msk [1/4]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1127 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Msk [2/4]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1043 of file core_armv8mml.h.

◆ ITM_STIM_DISABLED_Msk [3/4]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1043 of file core_cm33.h.

◆ ITM_STIM_DISABLED_Msk [4/4]

#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)

ITM STIM: DISABLED Mask

Definition at line 1043 of file core_cm35p.h.

◆ ITM_STIM_DISABLED_Pos [1/4]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1126 of file core_armv81mml.h.

◆ ITM_STIM_DISABLED_Pos [2/4]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1042 of file core_armv8mml.h.

◆ ITM_STIM_DISABLED_Pos [3/4]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1042 of file core_cm33.h.

◆ ITM_STIM_DISABLED_Pos [4/4]

#define ITM_STIM_DISABLED_Pos 1U

ITM STIM: DISABLED Position

Definition at line 1042 of file core_cm35p.h.

◆ ITM_STIM_FIFOREADY_Msk [1/4]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1130 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Msk [2/4]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1046 of file core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Msk [3/4]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1046 of file core_cm33.h.

◆ ITM_STIM_FIFOREADY_Msk [4/4]

#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)

ITM STIM: FIFOREADY Mask

Definition at line 1046 of file core_cm35p.h.

◆ ITM_STIM_FIFOREADY_Pos [1/4]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1129 of file core_armv81mml.h.

◆ ITM_STIM_FIFOREADY_Pos [2/4]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1045 of file core_armv8mml.h.

◆ ITM_STIM_FIFOREADY_Pos [3/4]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1045 of file core_cm33.h.

◆ ITM_STIM_FIFOREADY_Pos [4/4]

#define ITM_STIM_FIFOREADY_Pos 0U

ITM STIM: FIFOREADY Position

Definition at line 1045 of file core_cm35p.h.

◆ ITM_TCR_BUSY_Msk [1/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1138 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Msk [2/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1054 of file core_armv8mml.h.

◆ ITM_TCR_BUSY_Msk [3/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 792 of file core_cm3.h.

◆ ITM_TCR_BUSY_Msk [4/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1054 of file core_cm33.h.

◆ ITM_TCR_BUSY_Msk [5/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1054 of file core_cm35p.h.

◆ ITM_TCR_BUSY_Msk [6/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 850 of file core_cm4.h.

◆ ITM_TCR_BUSY_Msk [7/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 1070 of file core_cm7.h.

◆ ITM_TCR_BUSY_Msk [8/8]

#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)

ITM TCR: BUSY Mask

Definition at line 777 of file core_sc300.h.

◆ ITM_TCR_BUSY_Pos [1/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1137 of file core_armv81mml.h.

◆ ITM_TCR_BUSY_Pos [2/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1053 of file core_armv8mml.h.

◆ ITM_TCR_BUSY_Pos [3/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 791 of file core_cm3.h.

◆ ITM_TCR_BUSY_Pos [4/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1053 of file core_cm33.h.

◆ ITM_TCR_BUSY_Pos [5/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1053 of file core_cm35p.h.

◆ ITM_TCR_BUSY_Pos [6/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 849 of file core_cm4.h.

◆ ITM_TCR_BUSY_Pos [7/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 1069 of file core_cm7.h.

◆ ITM_TCR_BUSY_Pos [8/8]

#define ITM_TCR_BUSY_Pos 23U

ITM TCR: BUSY Position

Definition at line 776 of file core_sc300.h.

◆ ITM_TCR_DWTENA_Msk [1/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1156 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Msk [2/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1072 of file core_armv8mml.h.

◆ ITM_TCR_DWTENA_Msk [3/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 807 of file core_cm3.h.

◆ ITM_TCR_DWTENA_Msk [4/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1072 of file core_cm33.h.

◆ ITM_TCR_DWTENA_Msk [5/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1072 of file core_cm35p.h.

◆ ITM_TCR_DWTENA_Msk [6/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 865 of file core_cm4.h.

◆ ITM_TCR_DWTENA_Msk [7/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 1085 of file core_cm7.h.

◆ ITM_TCR_DWTENA_Msk [8/8]

#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)

ITM TCR: DWTENA Mask

Definition at line 792 of file core_sc300.h.

◆ ITM_TCR_DWTENA_Pos [1/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1155 of file core_armv81mml.h.

◆ ITM_TCR_DWTENA_Pos [2/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1071 of file core_armv8mml.h.

◆ ITM_TCR_DWTENA_Pos [3/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 806 of file core_cm3.h.

◆ ITM_TCR_DWTENA_Pos [4/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1071 of file core_cm33.h.

◆ ITM_TCR_DWTENA_Pos [5/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1071 of file core_cm35p.h.

◆ ITM_TCR_DWTENA_Pos [6/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 864 of file core_cm4.h.

◆ ITM_TCR_DWTENA_Pos [7/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 1084 of file core_cm7.h.

◆ ITM_TCR_DWTENA_Pos [8/8]

#define ITM_TCR_DWTENA_Pos 3U

ITM TCR: DWTENA Position

Definition at line 791 of file core_sc300.h.

◆ ITM_TCR_GTSFREQ_Msk [1/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1144 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Msk [2/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1060 of file core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Msk [3/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 798 of file core_cm3.h.

◆ ITM_TCR_GTSFREQ_Msk [4/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1060 of file core_cm33.h.

◆ ITM_TCR_GTSFREQ_Msk [5/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1060 of file core_cm35p.h.

◆ ITM_TCR_GTSFREQ_Msk [6/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 856 of file core_cm4.h.

◆ ITM_TCR_GTSFREQ_Msk [7/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 1076 of file core_cm7.h.

◆ ITM_TCR_GTSFREQ_Msk [8/8]

#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)

ITM TCR: Global timestamp frequency Mask

Definition at line 783 of file core_sc300.h.

◆ ITM_TCR_GTSFREQ_Pos [1/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1143 of file core_armv81mml.h.

◆ ITM_TCR_GTSFREQ_Pos [2/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1059 of file core_armv8mml.h.

◆ ITM_TCR_GTSFREQ_Pos [3/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 797 of file core_cm3.h.

◆ ITM_TCR_GTSFREQ_Pos [4/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1059 of file core_cm33.h.

◆ ITM_TCR_GTSFREQ_Pos [5/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1059 of file core_cm35p.h.

◆ ITM_TCR_GTSFREQ_Pos [6/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 855 of file core_cm4.h.

◆ ITM_TCR_GTSFREQ_Pos [7/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 1075 of file core_cm7.h.

◆ ITM_TCR_GTSFREQ_Pos [8/8]

#define ITM_TCR_GTSFREQ_Pos 10U

ITM TCR: Global timestamp frequency Position

Definition at line 782 of file core_sc300.h.

◆ ITM_TCR_ITMENA_Msk [1/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1165 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Msk [2/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1081 of file core_armv8mml.h.

◆ ITM_TCR_ITMENA_Msk [3/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 816 of file core_cm3.h.

◆ ITM_TCR_ITMENA_Msk [4/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1081 of file core_cm33.h.

◆ ITM_TCR_ITMENA_Msk [5/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1081 of file core_cm35p.h.

◆ ITM_TCR_ITMENA_Msk [6/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 874 of file core_cm4.h.

◆ ITM_TCR_ITMENA_Msk [7/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 1094 of file core_cm7.h.

◆ ITM_TCR_ITMENA_Msk [8/8]

#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)

ITM TCR: ITM Enable bit Mask

Definition at line 801 of file core_sc300.h.

◆ ITM_TCR_ITMENA_Pos [1/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1164 of file core_armv81mml.h.

◆ ITM_TCR_ITMENA_Pos [2/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1080 of file core_armv8mml.h.

◆ ITM_TCR_ITMENA_Pos [3/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 815 of file core_cm3.h.

◆ ITM_TCR_ITMENA_Pos [4/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1080 of file core_cm33.h.

◆ ITM_TCR_ITMENA_Pos [5/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1080 of file core_cm35p.h.

◆ ITM_TCR_ITMENA_Pos [6/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 873 of file core_cm4.h.

◆ ITM_TCR_ITMENA_Pos [7/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 1093 of file core_cm7.h.

◆ ITM_TCR_ITMENA_Pos [8/8]

#define ITM_TCR_ITMENA_Pos 0U

ITM TCR: ITM Enable bit Position

Definition at line 800 of file core_sc300.h.

◆ ITM_TCR_STALLENA_Msk [1/4]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1150 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Msk [2/4]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1066 of file core_armv8mml.h.

◆ ITM_TCR_STALLENA_Msk [3/4]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1066 of file core_cm33.h.

◆ ITM_TCR_STALLENA_Msk [4/4]

#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)

ITM TCR: STALLENA Mask

Definition at line 1066 of file core_cm35p.h.

◆ ITM_TCR_STALLENA_Pos [1/4]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1149 of file core_armv81mml.h.

◆ ITM_TCR_STALLENA_Pos [2/4]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1065 of file core_armv8mml.h.

◆ ITM_TCR_STALLENA_Pos [3/4]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1065 of file core_cm33.h.

◆ ITM_TCR_STALLENA_Pos [4/4]

#define ITM_TCR_STALLENA_Pos 5U

ITM TCR: STALLENA Position

Definition at line 1065 of file core_cm35p.h.

◆ ITM_TCR_SWOENA_Msk [1/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1153 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Msk [2/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1069 of file core_armv8mml.h.

◆ ITM_TCR_SWOENA_Msk [3/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 804 of file core_cm3.h.

◆ ITM_TCR_SWOENA_Msk [4/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1069 of file core_cm33.h.

◆ ITM_TCR_SWOENA_Msk [5/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1069 of file core_cm35p.h.

◆ ITM_TCR_SWOENA_Msk [6/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 862 of file core_cm4.h.

◆ ITM_TCR_SWOENA_Msk [7/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 1082 of file core_cm7.h.

◆ ITM_TCR_SWOENA_Msk [8/8]

#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)

ITM TCR: SWOENA Mask

Definition at line 789 of file core_sc300.h.

◆ ITM_TCR_SWOENA_Pos [1/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1152 of file core_armv81mml.h.

◆ ITM_TCR_SWOENA_Pos [2/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1068 of file core_armv8mml.h.

◆ ITM_TCR_SWOENA_Pos [3/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 803 of file core_cm3.h.

◆ ITM_TCR_SWOENA_Pos [4/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1068 of file core_cm33.h.

◆ ITM_TCR_SWOENA_Pos [5/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1068 of file core_cm35p.h.

◆ ITM_TCR_SWOENA_Pos [6/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 861 of file core_cm4.h.

◆ ITM_TCR_SWOENA_Pos [7/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 1081 of file core_cm7.h.

◆ ITM_TCR_SWOENA_Pos [8/8]

#define ITM_TCR_SWOENA_Pos 4U

ITM TCR: SWOENA Position

Definition at line 788 of file core_sc300.h.

◆ ITM_TCR_SYNCENA_Msk [1/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1159 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Msk [2/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1075 of file core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Msk [3/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 810 of file core_cm3.h.

◆ ITM_TCR_SYNCENA_Msk [4/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1075 of file core_cm33.h.

◆ ITM_TCR_SYNCENA_Msk [5/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1075 of file core_cm35p.h.

◆ ITM_TCR_SYNCENA_Msk [6/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 868 of file core_cm4.h.

◆ ITM_TCR_SYNCENA_Msk [7/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 1088 of file core_cm7.h.

◆ ITM_TCR_SYNCENA_Msk [8/8]

#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)

ITM TCR: SYNCENA Mask

Definition at line 795 of file core_sc300.h.

◆ ITM_TCR_SYNCENA_Pos [1/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1158 of file core_armv81mml.h.

◆ ITM_TCR_SYNCENA_Pos [2/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1074 of file core_armv8mml.h.

◆ ITM_TCR_SYNCENA_Pos [3/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 809 of file core_cm3.h.

◆ ITM_TCR_SYNCENA_Pos [4/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1074 of file core_cm33.h.

◆ ITM_TCR_SYNCENA_Pos [5/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1074 of file core_cm35p.h.

◆ ITM_TCR_SYNCENA_Pos [6/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 867 of file core_cm4.h.

◆ ITM_TCR_SYNCENA_Pos [7/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 1087 of file core_cm7.h.

◆ ITM_TCR_SYNCENA_Pos [8/8]

#define ITM_TCR_SYNCENA_Pos 2U

ITM TCR: SYNCENA Position

Definition at line 794 of file core_sc300.h.

◆ ITM_TCR_TRACEBUSID_Msk [1/4]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1141 of file core_armv81mml.h.

◆ ITM_TCR_TRACEBUSID_Msk [2/4]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1057 of file core_armv8mml.h.

◆ ITM_TCR_TraceBusID_Msk [1/4]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 795 of file core_cm3.h.

◆ ITM_TCR_TRACEBUSID_Msk [3/4]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1057 of file core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Msk [4/4]

#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)

ITM TCR: ATBID Mask

Definition at line 1057 of file core_cm35p.h.

◆ ITM_TCR_TraceBusID_Msk [2/4]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 853 of file core_cm4.h.

◆ ITM_TCR_TraceBusID_Msk [3/4]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 1073 of file core_cm7.h.

◆ ITM_TCR_TraceBusID_Msk [4/4]

#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)

ITM TCR: ATBID Mask

Definition at line 780 of file core_sc300.h.

◆ ITM_TCR_TRACEBUSID_Pos [1/4]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1140 of file core_armv81mml.h.

◆ ITM_TCR_TRACEBUSID_Pos [2/4]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1056 of file core_armv8mml.h.

◆ ITM_TCR_TraceBusID_Pos [1/4]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 794 of file core_cm3.h.

◆ ITM_TCR_TRACEBUSID_Pos [3/4]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1056 of file core_cm33.h.

◆ ITM_TCR_TRACEBUSID_Pos [4/4]

#define ITM_TCR_TRACEBUSID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1056 of file core_cm35p.h.

◆ ITM_TCR_TraceBusID_Pos [2/4]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 852 of file core_cm4.h.

◆ ITM_TCR_TraceBusID_Pos [3/4]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 1072 of file core_cm7.h.

◆ ITM_TCR_TraceBusID_Pos [4/4]

#define ITM_TCR_TraceBusID_Pos 16U

ITM TCR: ATBID Position

Definition at line 779 of file core_sc300.h.

◆ ITM_TCR_TSENA_Msk [1/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1162 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Msk [2/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1078 of file core_armv8mml.h.

◆ ITM_TCR_TSENA_Msk [3/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 813 of file core_cm3.h.

◆ ITM_TCR_TSENA_Msk [4/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1078 of file core_cm33.h.

◆ ITM_TCR_TSENA_Msk [5/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1078 of file core_cm35p.h.

◆ ITM_TCR_TSENA_Msk [6/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 871 of file core_cm4.h.

◆ ITM_TCR_TSENA_Msk [7/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 1091 of file core_cm7.h.

◆ ITM_TCR_TSENA_Msk [8/8]

#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)

ITM TCR: TSENA Mask

Definition at line 798 of file core_sc300.h.

◆ ITM_TCR_TSENA_Pos [1/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1161 of file core_armv81mml.h.

◆ ITM_TCR_TSENA_Pos [2/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1077 of file core_armv8mml.h.

◆ ITM_TCR_TSENA_Pos [3/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 812 of file core_cm3.h.

◆ ITM_TCR_TSENA_Pos [4/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1077 of file core_cm33.h.

◆ ITM_TCR_TSENA_Pos [5/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1077 of file core_cm35p.h.

◆ ITM_TCR_TSENA_Pos [6/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 870 of file core_cm4.h.

◆ ITM_TCR_TSENA_Pos [7/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 1090 of file core_cm7.h.

◆ ITM_TCR_TSENA_Pos [8/8]

#define ITM_TCR_TSENA_Pos 1U

ITM TCR: TSENA Position

Definition at line 797 of file core_sc300.h.

◆ ITM_TCR_TSPRESCALE_Msk [1/4]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1147 of file core_armv81mml.h.

◆ ITM_TCR_TSPRESCALE_Msk [2/4]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1063 of file core_armv8mml.h.

◆ ITM_TCR_TSPrescale_Msk [1/4]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 801 of file core_cm3.h.

◆ ITM_TCR_TSPRESCALE_Msk [3/4]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1063 of file core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Msk [4/4]

#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)

ITM TCR: TSPRESCALE Mask

Definition at line 1063 of file core_cm35p.h.

◆ ITM_TCR_TSPrescale_Msk [2/4]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 859 of file core_cm4.h.

◆ ITM_TCR_TSPrescale_Msk [3/4]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 1079 of file core_cm7.h.

◆ ITM_TCR_TSPrescale_Msk [4/4]

#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)

ITM TCR: TSPrescale Mask

Definition at line 786 of file core_sc300.h.

◆ ITM_TCR_TSPRESCALE_Pos [1/4]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1146 of file core_armv81mml.h.

◆ ITM_TCR_TSPRESCALE_Pos [2/4]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1062 of file core_armv8mml.h.

◆ ITM_TCR_TSPrescale_Pos [1/4]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 800 of file core_cm3.h.

◆ ITM_TCR_TSPRESCALE_Pos [3/4]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1062 of file core_cm33.h.

◆ ITM_TCR_TSPRESCALE_Pos [4/4]

#define ITM_TCR_TSPRESCALE_Pos 8U

ITM TCR: TSPRESCALE Position

Definition at line 1062 of file core_cm35p.h.

◆ ITM_TCR_TSPrescale_Pos [2/4]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 858 of file core_cm4.h.

◆ ITM_TCR_TSPrescale_Pos [3/4]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 1078 of file core_cm7.h.

◆ ITM_TCR_TSPrescale_Pos [4/4]

#define ITM_TCR_TSPrescale_Pos 8U

ITM TCR: TSPrescale Position

Definition at line 785 of file core_sc300.h.

◆ ITM_TPR_PRIVMASK_Msk [1/8]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1134 of file core_armv81mml.h.

◆ ITM_TPR_PRIVMASK_Msk [2/8]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1050 of file core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Msk [3/8]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 788 of file core_cm3.h.

◆ ITM_TPR_PRIVMASK_Msk [4/8]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1050 of file core_cm33.h.

◆ ITM_TPR_PRIVMASK_Msk [5/8]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1050 of file core_cm35p.h.

◆ ITM_TPR_PRIVMASK_Msk [6/8]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 846 of file core_cm4.h.

◆ ITM_TPR_PRIVMASK_Msk [7/8]

#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 1066 of file core_cm7.h.

◆ ITM_TPR_PRIVMASK_Msk [8/8]

#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)

ITM TPR: PRIVMASK Mask

Definition at line 773 of file core_sc300.h.

◆ ITM_TPR_PRIVMASK_Pos [1/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1133 of file core_armv81mml.h.

◆ ITM_TPR_PRIVMASK_Pos [2/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1049 of file core_armv8mml.h.

◆ ITM_TPR_PRIVMASK_Pos [3/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 787 of file core_cm3.h.

◆ ITM_TPR_PRIVMASK_Pos [4/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1049 of file core_cm33.h.

◆ ITM_TPR_PRIVMASK_Pos [5/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1049 of file core_cm35p.h.

◆ ITM_TPR_PRIVMASK_Pos [6/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 845 of file core_cm4.h.

◆ ITM_TPR_PRIVMASK_Pos [7/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 1065 of file core_cm7.h.

◆ ITM_TPR_PRIVMASK_Pos [8/8]

#define ITM_TPR_PRIVMASK_Pos 0U

ITM TPR: PRIVMASK Position

Definition at line 772 of file core_sc300.h.

◆ NVIC [1/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 2046 of file core_armv81mml.h.

◆ NVIC [2/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1124 of file core_armv8mbl.h.

◆ NVIC [3/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1890 of file core_armv8mml.h.

◆ NVIC [4/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 541 of file core_cm0.h.

◆ NVIC [5/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 655 of file core_cm0plus.h.

◆ NVIC [6/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 568 of file core_cm1.h.

◆ NVIC [7/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1199 of file core_cm23.h.

◆ NVIC [8/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1387 of file core_cm3.h.

◆ NVIC [9/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1965 of file core_cm33.h.

◆ NVIC [10/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1965 of file core_cm35p.h.

◆ NVIC [11/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1557 of file core_cm4.h.

◆ NVIC [12/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1780 of file core_cm7.h.

◆ NVIC [13/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 665 of file core_sc000.h.

◆ NVIC [14/14]

#define NVIC ((NVIC_Type *) NVIC_BASE )

NVIC configuration struct

Definition at line 1370 of file core_sc300.h.

◆ NVIC_BASE [1/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 2040 of file core_armv81mml.h.

◆ NVIC_BASE [2/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1118 of file core_armv8mbl.h.

◆ NVIC_BASE [3/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1884 of file core_armv8mml.h.

◆ NVIC_BASE [4/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 536 of file core_cm0.h.

◆ NVIC_BASE [5/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 650 of file core_cm0plus.h.

◆ NVIC_BASE [6/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 562 of file core_cm1.h.

◆ NVIC_BASE [7/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1193 of file core_cm23.h.

◆ NVIC_BASE [8/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1381 of file core_cm3.h.

◆ NVIC_BASE [9/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1959 of file core_cm33.h.

◆ NVIC_BASE [10/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1959 of file core_cm35p.h.

◆ NVIC_BASE [11/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1551 of file core_cm4.h.

◆ NVIC_BASE [12/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1774 of file core_cm7.h.

◆ NVIC_BASE [13/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 659 of file core_sc000.h.

◆ NVIC_BASE [14/14]

#define NVIC_BASE (SCS_BASE + 0x0100UL)

NVIC Base Address

Definition at line 1364 of file core_sc300.h.

◆ NVIC_ClearPendingIRQ [1/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 2126 of file core_armv81mml.h.

◆ NVIC_ClearPendingIRQ [2/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 1195 of file core_armv8mbl.h.

◆ NVIC_ClearPendingIRQ [3/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 1970 of file core_armv8mml.h.

◆ NVIC_ClearPendingIRQ [4/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 582 of file core_cm0.h.

◆ NVIC_ClearPendingIRQ [5/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 700 of file core_cm0plus.h.

◆ NVIC_ClearPendingIRQ [6/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 609 of file core_cm1.h.

◆ NVIC_ClearPendingIRQ [7/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 1270 of file core_cm23.h.

◆ NVIC_ClearPendingIRQ [8/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 1437 of file core_cm3.h.

◆ NVIC_ClearPendingIRQ [9/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 2045 of file core_cm33.h.

◆ NVIC_ClearPendingIRQ [10/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 2045 of file core_cm35p.h.

◆ NVIC_ClearPendingIRQ [11/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 1610 of file core_cm4.h.

◆ NVIC_ClearPendingIRQ [12/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 1833 of file core_cm7.h.

◆ NVIC_ClearPendingIRQ [13/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 710 of file core_sc000.h.

◆ NVIC_ClearPendingIRQ [14/14]

#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ

Definition at line 1420 of file core_sc300.h.

◆ NVIC_DisableIRQ [1/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 2123 of file core_armv81mml.h.

◆ NVIC_DisableIRQ [2/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 1192 of file core_armv8mbl.h.

◆ NVIC_DisableIRQ [3/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 1967 of file core_armv8mml.h.

◆ NVIC_DisableIRQ [4/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 579 of file core_cm0.h.

◆ NVIC_DisableIRQ [5/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 697 of file core_cm0plus.h.

◆ NVIC_DisableIRQ [6/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 606 of file core_cm1.h.

◆ NVIC_DisableIRQ [7/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 1267 of file core_cm23.h.

◆ NVIC_DisableIRQ [8/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 1434 of file core_cm3.h.

◆ NVIC_DisableIRQ [9/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 2042 of file core_cm33.h.

◆ NVIC_DisableIRQ [10/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 2042 of file core_cm35p.h.

◆ NVIC_DisableIRQ [11/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 1607 of file core_cm4.h.

◆ NVIC_DisableIRQ [12/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 1830 of file core_cm7.h.

◆ NVIC_DisableIRQ [13/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 707 of file core_sc000.h.

◆ NVIC_DisableIRQ [14/14]

#define NVIC_DisableIRQ __NVIC_DisableIRQ

Definition at line 1417 of file core_sc300.h.

◆ NVIC_EnableIRQ [1/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 2121 of file core_armv81mml.h.

◆ NVIC_EnableIRQ [2/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 1190 of file core_armv8mbl.h.

◆ NVIC_EnableIRQ [3/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 1965 of file core_armv8mml.h.

◆ NVIC_EnableIRQ [4/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 577 of file core_cm0.h.

◆ NVIC_EnableIRQ [5/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 695 of file core_cm0plus.h.

◆ NVIC_EnableIRQ [6/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 604 of file core_cm1.h.

◆ NVIC_EnableIRQ [7/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 1265 of file core_cm23.h.

◆ NVIC_EnableIRQ [8/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 1432 of file core_cm3.h.

◆ NVIC_EnableIRQ [9/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 2040 of file core_cm33.h.

◆ NVIC_EnableIRQ [10/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 2040 of file core_cm35p.h.

◆ NVIC_EnableIRQ [11/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 1605 of file core_cm4.h.

◆ NVIC_EnableIRQ [12/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 1828 of file core_cm7.h.

◆ NVIC_EnableIRQ [13/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 705 of file core_sc000.h.

◆ NVIC_EnableIRQ [14/14]

#define NVIC_EnableIRQ __NVIC_EnableIRQ

Definition at line 1415 of file core_sc300.h.

◆ NVIC_GetActive [1/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 2127 of file core_armv81mml.h.

◆ NVIC_GetActive [2/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 1196 of file core_armv8mbl.h.

◆ NVIC_GetActive [3/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 1971 of file core_armv8mml.h.

◆ NVIC_GetActive [4/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 1271 of file core_cm23.h.

◆ NVIC_GetActive [5/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 1438 of file core_cm3.h.

◆ NVIC_GetActive [6/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 2046 of file core_cm33.h.

◆ NVIC_GetActive [7/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 2046 of file core_cm35p.h.

◆ NVIC_GetActive [8/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 1611 of file core_cm4.h.

◆ NVIC_GetActive [9/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 1834 of file core_cm7.h.

◆ NVIC_GetActive [10/10]

#define NVIC_GetActive __NVIC_GetActive

Definition at line 1421 of file core_sc300.h.

◆ NVIC_GetEnableIRQ [1/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 2122 of file core_armv81mml.h.

◆ NVIC_GetEnableIRQ [2/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 1191 of file core_armv8mbl.h.

◆ NVIC_GetEnableIRQ [3/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 1966 of file core_armv8mml.h.

◆ NVIC_GetEnableIRQ [4/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 578 of file core_cm0.h.

◆ NVIC_GetEnableIRQ [5/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 696 of file core_cm0plus.h.

◆ NVIC_GetEnableIRQ [6/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 605 of file core_cm1.h.

◆ NVIC_GetEnableIRQ [7/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 1266 of file core_cm23.h.

◆ NVIC_GetEnableIRQ [8/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 1433 of file core_cm3.h.

◆ NVIC_GetEnableIRQ [9/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 2041 of file core_cm33.h.

◆ NVIC_GetEnableIRQ [10/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 2041 of file core_cm35p.h.

◆ NVIC_GetEnableIRQ [11/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 1606 of file core_cm4.h.

◆ NVIC_GetEnableIRQ [12/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 1829 of file core_cm7.h.

◆ NVIC_GetEnableIRQ [13/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 706 of file core_sc000.h.

◆ NVIC_GetEnableIRQ [14/14]

#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ

Definition at line 1416 of file core_sc300.h.

◆ NVIC_GetPendingIRQ [1/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 2124 of file core_armv81mml.h.

◆ NVIC_GetPendingIRQ [2/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 1193 of file core_armv8mbl.h.

◆ NVIC_GetPendingIRQ [3/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 1968 of file core_armv8mml.h.

◆ NVIC_GetPendingIRQ [4/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 580 of file core_cm0.h.

◆ NVIC_GetPendingIRQ [5/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 698 of file core_cm0plus.h.

◆ NVIC_GetPendingIRQ [6/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 607 of file core_cm1.h.

◆ NVIC_GetPendingIRQ [7/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 1268 of file core_cm23.h.

◆ NVIC_GetPendingIRQ [8/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 1435 of file core_cm3.h.

◆ NVIC_GetPendingIRQ [9/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 2043 of file core_cm33.h.

◆ NVIC_GetPendingIRQ [10/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 2043 of file core_cm35p.h.

◆ NVIC_GetPendingIRQ [11/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 1608 of file core_cm4.h.

◆ NVIC_GetPendingIRQ [12/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 1831 of file core_cm7.h.

◆ NVIC_GetPendingIRQ [13/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 708 of file core_sc000.h.

◆ NVIC_GetPendingIRQ [14/14]

#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ

Definition at line 1418 of file core_sc300.h.

◆ NVIC_GetPriority [1/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 2129 of file core_armv81mml.h.

◆ NVIC_GetPriority [2/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 1198 of file core_armv8mbl.h.

◆ NVIC_GetPriority [3/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 1973 of file core_armv8mml.h.

◆ NVIC_GetPriority [4/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 585 of file core_cm0.h.

◆ NVIC_GetPriority [5/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 703 of file core_cm0plus.h.

◆ NVIC_GetPriority [6/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 612 of file core_cm1.h.

◆ NVIC_GetPriority [7/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 1273 of file core_cm23.h.

◆ NVIC_GetPriority [8/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 1440 of file core_cm3.h.

◆ NVIC_GetPriority [9/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 2048 of file core_cm33.h.

◆ NVIC_GetPriority [10/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 2048 of file core_cm35p.h.

◆ NVIC_GetPriority [11/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 1613 of file core_cm4.h.

◆ NVIC_GetPriority [12/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 1836 of file core_cm7.h.

◆ NVIC_GetPriority [13/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 713 of file core_sc000.h.

◆ NVIC_GetPriority [14/14]

#define NVIC_GetPriority __NVIC_GetPriority

Definition at line 1423 of file core_sc300.h.

◆ NVIC_GetPriorityGrouping [1/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 2120 of file core_armv81mml.h.

◆ NVIC_GetPriorityGrouping [2/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 1189 of file core_armv8mbl.h.

◆ NVIC_GetPriorityGrouping [3/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 1964 of file core_armv8mml.h.

◆ NVIC_GetPriorityGrouping [4/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 576 of file core_cm0.h.

◆ NVIC_GetPriorityGrouping [5/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 694 of file core_cm0plus.h.

◆ NVIC_GetPriorityGrouping [6/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 603 of file core_cm1.h.

◆ NVIC_GetPriorityGrouping [7/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 1431 of file core_cm3.h.

◆ NVIC_GetPriorityGrouping [8/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 2039 of file core_cm33.h.

◆ NVIC_GetPriorityGrouping [9/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 2039 of file core_cm35p.h.

◆ NVIC_GetPriorityGrouping [10/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 1604 of file core_cm4.h.

◆ NVIC_GetPriorityGrouping [11/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 1827 of file core_cm7.h.

◆ NVIC_GetPriorityGrouping [12/12]

#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping

Definition at line 1414 of file core_sc300.h.

◆ NVIC_GetVector [1/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 2140 of file core_armv81mml.h.

◆ NVIC_GetVector [2/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 1209 of file core_armv8mbl.h.

◆ NVIC_GetVector [3/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 1984 of file core_armv8mml.h.

◆ NVIC_GetVector [4/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 596 of file core_cm0.h.

◆ NVIC_GetVector [5/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 714 of file core_cm0plus.h.

◆ NVIC_GetVector [6/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 623 of file core_cm1.h.

◆ NVIC_GetVector [7/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 1284 of file core_cm23.h.

◆ NVIC_GetVector [8/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 1451 of file core_cm3.h.

◆ NVIC_GetVector [9/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 2059 of file core_cm33.h.

◆ NVIC_GetVector [10/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 2059 of file core_cm35p.h.

◆ NVIC_GetVector [11/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 1624 of file core_cm4.h.

◆ NVIC_GetVector [12/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 1847 of file core_cm7.h.

◆ NVIC_GetVector [13/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 724 of file core_sc000.h.

◆ NVIC_GetVector [14/14]

#define NVIC_GetVector __NVIC_GetVector

Definition at line 1434 of file core_sc300.h.

◆ NVIC_SetPendingIRQ [1/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 2125 of file core_armv81mml.h.

◆ NVIC_SetPendingIRQ [2/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 1194 of file core_armv8mbl.h.

◆ NVIC_SetPendingIRQ [3/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 1969 of file core_armv8mml.h.

◆ NVIC_SetPendingIRQ [4/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 581 of file core_cm0.h.

◆ NVIC_SetPendingIRQ [5/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 699 of file core_cm0plus.h.

◆ NVIC_SetPendingIRQ [6/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 608 of file core_cm1.h.

◆ NVIC_SetPendingIRQ [7/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 1269 of file core_cm23.h.

◆ NVIC_SetPendingIRQ [8/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 1436 of file core_cm3.h.

◆ NVIC_SetPendingIRQ [9/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 2044 of file core_cm33.h.

◆ NVIC_SetPendingIRQ [10/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 2044 of file core_cm35p.h.

◆ NVIC_SetPendingIRQ [11/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 1609 of file core_cm4.h.

◆ NVIC_SetPendingIRQ [12/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 1832 of file core_cm7.h.

◆ NVIC_SetPendingIRQ [13/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 709 of file core_sc000.h.

◆ NVIC_SetPendingIRQ [14/14]

#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ

Definition at line 1419 of file core_sc300.h.

◆ NVIC_SetPriority [1/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 2128 of file core_armv81mml.h.

◆ NVIC_SetPriority [2/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 1197 of file core_armv8mbl.h.

◆ NVIC_SetPriority [3/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 1972 of file core_armv8mml.h.

◆ NVIC_SetPriority [4/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 584 of file core_cm0.h.

◆ NVIC_SetPriority [5/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 702 of file core_cm0plus.h.

◆ NVIC_SetPriority [6/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 611 of file core_cm1.h.

◆ NVIC_SetPriority [7/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 1272 of file core_cm23.h.

◆ NVIC_SetPriority [8/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 1439 of file core_cm3.h.

◆ NVIC_SetPriority [9/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 2047 of file core_cm33.h.

◆ NVIC_SetPriority [10/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 2047 of file core_cm35p.h.

◆ NVIC_SetPriority [11/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 1612 of file core_cm4.h.

◆ NVIC_SetPriority [12/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 1835 of file core_cm7.h.

◆ NVIC_SetPriority [13/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 712 of file core_sc000.h.

◆ NVIC_SetPriority [14/14]

#define NVIC_SetPriority __NVIC_SetPriority

Definition at line 1422 of file core_sc300.h.

◆ NVIC_SetPriorityGrouping [1/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 2119 of file core_armv81mml.h.

◆ NVIC_SetPriorityGrouping [2/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 1188 of file core_armv8mbl.h.

◆ NVIC_SetPriorityGrouping [3/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 1963 of file core_armv8mml.h.

◆ NVIC_SetPriorityGrouping [4/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 575 of file core_cm0.h.

◆ NVIC_SetPriorityGrouping [5/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 693 of file core_cm0plus.h.

◆ NVIC_SetPriorityGrouping [6/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 602 of file core_cm1.h.

◆ NVIC_SetPriorityGrouping [7/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 1430 of file core_cm3.h.

◆ NVIC_SetPriorityGrouping [8/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 2038 of file core_cm33.h.

◆ NVIC_SetPriorityGrouping [9/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 2038 of file core_cm35p.h.

◆ NVIC_SetPriorityGrouping [10/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 1603 of file core_cm4.h.

◆ NVIC_SetPriorityGrouping [11/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 1826 of file core_cm7.h.

◆ NVIC_SetPriorityGrouping [12/12]

#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping

Definition at line 1413 of file core_sc300.h.

◆ NVIC_SetVector [1/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 2139 of file core_armv81mml.h.

◆ NVIC_SetVector [2/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 1208 of file core_armv8mbl.h.

◆ NVIC_SetVector [3/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 1983 of file core_armv8mml.h.

◆ NVIC_SetVector [4/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 595 of file core_cm0.h.

◆ NVIC_SetVector [5/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 713 of file core_cm0plus.h.

◆ NVIC_SetVector [6/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 622 of file core_cm1.h.

◆ NVIC_SetVector [7/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 1283 of file core_cm23.h.

◆ NVIC_SetVector [8/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 1450 of file core_cm3.h.

◆ NVIC_SetVector [9/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 2058 of file core_cm33.h.

◆ NVIC_SetVector [10/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 2058 of file core_cm35p.h.

◆ NVIC_SetVector [11/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 1623 of file core_cm4.h.

◆ NVIC_SetVector [12/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 1846 of file core_cm7.h.

◆ NVIC_SetVector [13/14]

#define NVIC_SetVector __NVIC_SetVector

Definition at line 723 of file core_sc000.h.

◆ NVIC_SystemReset [1/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 2130 of file core_armv81mml.h.

◆ NVIC_SystemReset [2/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 1199 of file core_armv8mbl.h.

◆ NVIC_SystemReset [3/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 1974 of file core_armv8mml.h.

◆ NVIC_SystemReset [4/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 586 of file core_cm0.h.

◆ NVIC_SystemReset [5/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 704 of file core_cm0plus.h.

◆ NVIC_SystemReset [6/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 613 of file core_cm1.h.

◆ NVIC_SystemReset [7/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 1274 of file core_cm23.h.

◆ NVIC_SystemReset [8/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 1441 of file core_cm3.h.

◆ NVIC_SystemReset [9/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 2049 of file core_cm33.h.

◆ NVIC_SystemReset [10/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 2049 of file core_cm35p.h.

◆ NVIC_SystemReset [11/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 1614 of file core_cm4.h.

◆ NVIC_SystemReset [12/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 1837 of file core_cm7.h.

◆ NVIC_SystemReset [13/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 714 of file core_sc000.h.

◆ NVIC_SystemReset [14/14]

#define NVIC_SystemReset __NVIC_SystemReset

Definition at line 1424 of file core_sc300.h.

◆ NVIC_USER_IRQ_OFFSET [1/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 2143 of file core_armv81mml.h.

◆ NVIC_USER_IRQ_OFFSET [2/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 1212 of file core_armv8mbl.h.

◆ NVIC_USER_IRQ_OFFSET [3/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 1987 of file core_armv8mml.h.

◆ NVIC_USER_IRQ_OFFSET [4/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 599 of file core_cm0.h.

◆ NVIC_USER_IRQ_OFFSET [5/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 717 of file core_cm0plus.h.

◆ NVIC_USER_IRQ_OFFSET [6/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 626 of file core_cm1.h.

◆ NVIC_USER_IRQ_OFFSET [7/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 1287 of file core_cm23.h.

◆ NVIC_USER_IRQ_OFFSET [8/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 1454 of file core_cm3.h.

◆ NVIC_USER_IRQ_OFFSET [9/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 2062 of file core_cm33.h.

◆ NVIC_USER_IRQ_OFFSET [10/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 2062 of file core_cm35p.h.

◆ NVIC_USER_IRQ_OFFSET [11/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 1627 of file core_cm4.h.

◆ NVIC_USER_IRQ_OFFSET [12/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 1850 of file core_cm7.h.

◆ NVIC_USER_IRQ_OFFSET [13/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 727 of file core_sc000.h.

◆ NVIC_USER_IRQ_OFFSET [14/14]

#define NVIC_USER_IRQ_OFFSET 16

Definition at line 1437 of file core_sc300.h.

◆ SCB [1/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 2044 of file core_armv81mml.h.

◆ SCB [2/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1122 of file core_armv8mbl.h.

◆ SCB [3/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1888 of file core_armv8mml.h.

◆ SCB [4/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 539 of file core_cm0.h.

◆ SCB [5/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 653 of file core_cm0plus.h.

◆ SCB [6/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 566 of file core_cm1.h.

◆ SCB [7/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1197 of file core_cm23.h.

◆ SCB [8/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1385 of file core_cm3.h.

◆ SCB [9/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1963 of file core_cm33.h.

◆ SCB [10/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1963 of file core_cm35p.h.

◆ SCB [11/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1555 of file core_cm4.h.

◆ SCB [12/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1778 of file core_cm7.h.

◆ SCB [13/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 663 of file core_sc000.h.

◆ SCB [14/14]

#define SCB ((SCB_Type *) SCB_BASE )

SCB configuration struct

Definition at line 1368 of file core_sc300.h.

◆ SCB_ABFSR_AHBP_Msk [1/2]

#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 989 of file core_armv81mml.h.

◆ SCB_ABFSR_AHBP_Msk [2/2]

#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)

SCB ABFSR: AHBP Mask

Definition at line 900 of file core_cm7.h.

◆ SCB_ABFSR_AHBP_Pos [1/2]

#define SCB_ABFSR_AHBP_Pos 2U

SCB ABFSR: AHBP Position

Definition at line 988 of file core_armv81mml.h.

◆ SCB_ABFSR_AHBP_Pos [2/2]

#define SCB_ABFSR_AHBP_Pos 2U

SCB ABFSR: AHBP Position

Definition at line 899 of file core_cm7.h.

◆ SCB_ABFSR_AXIM_Msk [1/2]

#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 986 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIM_Msk [2/2]

#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)

SCB ABFSR: AXIM Mask

Definition at line 897 of file core_cm7.h.

◆ SCB_ABFSR_AXIM_Pos [1/2]

#define SCB_ABFSR_AXIM_Pos 3U

SCB ABFSR: AXIM Position

Definition at line 985 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIM_Pos [2/2]

#define SCB_ABFSR_AXIM_Pos 3U

SCB ABFSR: AXIM Position

Definition at line 896 of file core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [1/2]

#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 980 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIMTYPE_Msk [2/2]

#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)

SCB ABFSR: AXIMTYPE Mask

Definition at line 891 of file core_cm7.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [1/2]

#define SCB_ABFSR_AXIMTYPE_Pos 8U

SCB ABFSR: AXIMTYPE Position

Definition at line 979 of file core_armv81mml.h.

◆ SCB_ABFSR_AXIMTYPE_Pos [2/2]

#define SCB_ABFSR_AXIMTYPE_Pos 8U

SCB ABFSR: AXIMTYPE Position

Definition at line 890 of file core_cm7.h.

◆ SCB_ABFSR_DTCM_Msk [1/2]

#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 992 of file core_armv81mml.h.

◆ SCB_ABFSR_DTCM_Msk [2/2]

#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)

SCB ABFSR: DTCM Mask

Definition at line 903 of file core_cm7.h.

◆ SCB_ABFSR_DTCM_Pos [1/2]

#define SCB_ABFSR_DTCM_Pos 1U

SCB ABFSR: DTCM Position

Definition at line 991 of file core_armv81mml.h.

◆ SCB_ABFSR_DTCM_Pos [2/2]

#define SCB_ABFSR_DTCM_Pos 1U

SCB ABFSR: DTCM Position

Definition at line 902 of file core_cm7.h.

◆ SCB_ABFSR_EPPB_Msk [1/2]

#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 983 of file core_armv81mml.h.

◆ SCB_ABFSR_EPPB_Msk [2/2]

#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)

SCB ABFSR: EPPB Mask

Definition at line 894 of file core_cm7.h.

◆ SCB_ABFSR_EPPB_Pos [1/2]

#define SCB_ABFSR_EPPB_Pos 4U

SCB ABFSR: EPPB Position

Definition at line 982 of file core_armv81mml.h.

◆ SCB_ABFSR_EPPB_Pos [2/2]

#define SCB_ABFSR_EPPB_Pos 4U

SCB ABFSR: EPPB Position

Definition at line 893 of file core_cm7.h.

◆ SCB_ABFSR_ITCM_Msk [1/2]

#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 995 of file core_armv81mml.h.

◆ SCB_ABFSR_ITCM_Msk [2/2]

#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)

SCB ABFSR: ITCM Mask

Definition at line 906 of file core_cm7.h.

◆ SCB_ABFSR_ITCM_Pos [1/2]

#define SCB_ABFSR_ITCM_Pos 0U

SCB ABFSR: ITCM Position

Definition at line 994 of file core_armv81mml.h.

◆ SCB_ABFSR_ITCM_Pos [2/2]

#define SCB_ABFSR_ITCM_Pos 0U

SCB ABFSR: ITCM Position

Definition at line 905 of file core_cm7.h.

◆ SCB_AHBPCR_EN_Msk [1/2]

#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 956 of file core_armv81mml.h.

◆ SCB_AHBPCR_EN_Msk [2/2]

#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)

SCB AHBPCR: EN Mask

Definition at line 867 of file core_cm7.h.

◆ SCB_AHBPCR_EN_Pos [1/2]

#define SCB_AHBPCR_EN_Pos 0U

SCB AHBPCR: EN Position

Definition at line 955 of file core_armv81mml.h.

◆ SCB_AHBPCR_EN_Pos [2/2]

#define SCB_AHBPCR_EN_Pos 0U

SCB AHBPCR: EN Position

Definition at line 866 of file core_cm7.h.

◆ SCB_AHBPCR_SZ_Msk [1/2]

#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 953 of file core_armv81mml.h.

◆ SCB_AHBPCR_SZ_Msk [2/2]

#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)

SCB AHBPCR: SZ Mask

Definition at line 864 of file core_cm7.h.

◆ SCB_AHBPCR_SZ_Pos [1/2]

#define SCB_AHBPCR_SZ_Pos 1U

SCB AHBPCR: SZ Position

Definition at line 952 of file core_armv81mml.h.

◆ SCB_AHBPCR_SZ_Pos [2/2]

#define SCB_AHBPCR_SZ_Pos 1U

SCB AHBPCR: SZ Position

Definition at line 863 of file core_cm7.h.

◆ SCB_AHBSCR_CTL_Msk [1/2]

#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 976 of file core_armv81mml.h.

◆ SCB_AHBSCR_CTL_Msk [2/2]

#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)

SCB AHBSCR: CTL Mask

Definition at line 887 of file core_cm7.h.

◆ SCB_AHBSCR_CTL_Pos [1/2]

#define SCB_AHBSCR_CTL_Pos 0U

SCB AHBSCR: CTL Position

Definition at line 975 of file core_armv81mml.h.

◆ SCB_AHBSCR_CTL_Pos [2/2]

#define SCB_AHBSCR_CTL_Pos 0U

SCB AHBSCR: CTL Position

Definition at line 886 of file core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [1/2]

#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 970 of file core_armv81mml.h.

◆ SCB_AHBSCR_INITCOUNT_Msk [2/2]

#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)

SCB AHBSCR: INITCOUNT Mask

Definition at line 881 of file core_cm7.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [1/2]

#define SCB_AHBSCR_INITCOUNT_Pos 11U

SCB AHBSCR: INITCOUNT Position

Definition at line 969 of file core_armv81mml.h.

◆ SCB_AHBSCR_INITCOUNT_Pos [2/2]

#define SCB_AHBSCR_INITCOUNT_Pos 11U

SCB AHBSCR: INITCOUNT Position

Definition at line 880 of file core_cm7.h.

◆ SCB_AHBSCR_TPRI_Msk [1/2]

#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 973 of file core_armv81mml.h.

◆ SCB_AHBSCR_TPRI_Msk [2/2]

#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)

SCB AHBSCR: TPRI Mask

Definition at line 884 of file core_cm7.h.

◆ SCB_AHBSCR_TPRI_Pos [1/2]

#define SCB_AHBSCR_TPRI_Pos 2U

SCB AHBSCR: TPRI Position

Definition at line 972 of file core_armv81mml.h.

◆ SCB_AHBSCR_TPRI_Pos [2/2]

#define SCB_AHBSCR_TPRI_Pos 2U

SCB AHBSCR: TPRI Position

Definition at line 883 of file core_cm7.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [1/6]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 626 of file core_armv81mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [2/6]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [3/6]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 617 of file core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [4/6]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 474 of file core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [5/6]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 617 of file core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Msk [6/6]

#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)

SCB AIRCR: BFHFNMINS Mask

Definition at line 617 of file core_cm35p.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [1/6]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 625 of file core_armv81mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [2/6]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file core_armv8mbl.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [3/6]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 616 of file core_armv8mml.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [4/6]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 473 of file core_cm23.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [5/6]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 616 of file core_cm33.h.

◆ SCB_AIRCR_BFHFNMINS_Pos [6/6]

#define SCB_AIRCR_BFHFNMINS_Pos 13U

SCB AIRCR: BFHFNMINS Position

Definition at line 616 of file core_cm35p.h.

◆ SCB_AIRCR_ENDIANESS_Msk [1/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 620 of file core_armv81mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [2/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Msk [3/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 611 of file core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Msk [4/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Msk [5/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 430 of file core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Msk [6/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 406 of file core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Msk [7/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 468 of file core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Msk [8/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 466 of file core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Msk [9/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 611 of file core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Msk [10/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 611 of file core_cm35p.h.

◆ SCB_AIRCR_ENDIANESS_Msk [11/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 524 of file core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Msk [12/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 568 of file core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Msk [13/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 418 of file core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Msk [14/14]

#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)

SCB AIRCR: ENDIANESS Mask

Definition at line 463 of file core_sc300.h.

◆ SCB_AIRCR_ENDIANESS_Pos [1/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 619 of file core_armv81mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [2/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file core_armv8mbl.h.

◆ SCB_AIRCR_ENDIANESS_Pos [3/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 610 of file core_armv8mml.h.

◆ SCB_AIRCR_ENDIANESS_Pos [4/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file core_cm0.h.

◆ SCB_AIRCR_ENDIANESS_Pos [5/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 429 of file core_cm0plus.h.

◆ SCB_AIRCR_ENDIANESS_Pos [6/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 405 of file core_cm1.h.

◆ SCB_AIRCR_ENDIANESS_Pos [7/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 467 of file core_cm23.h.

◆ SCB_AIRCR_ENDIANESS_Pos [8/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 465 of file core_cm3.h.

◆ SCB_AIRCR_ENDIANESS_Pos [9/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 610 of file core_cm33.h.

◆ SCB_AIRCR_ENDIANESS_Pos [10/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 610 of file core_cm35p.h.

◆ SCB_AIRCR_ENDIANESS_Pos [11/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 523 of file core_cm4.h.

◆ SCB_AIRCR_ENDIANESS_Pos [12/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 567 of file core_cm7.h.

◆ SCB_AIRCR_ENDIANESS_Pos [13/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 417 of file core_sc000.h.

◆ SCB_AIRCR_ENDIANESS_Pos [14/14]

#define SCB_AIRCR_ENDIANESS_Pos 15U

SCB AIRCR: ENDIANESS Position

Definition at line 462 of file core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Msk [1/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 629 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [2/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 620 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Msk [3/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 469 of file core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Msk [4/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 620 of file core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Msk [5/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 620 of file core_cm35p.h.

◆ SCB_AIRCR_PRIGROUP_Msk [6/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 527 of file core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Msk [7/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 571 of file core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Msk [8/8]

#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)

SCB AIRCR: PRIGROUP Mask

Definition at line 466 of file core_sc300.h.

◆ SCB_AIRCR_PRIGROUP_Pos [1/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 628 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [2/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 619 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIGROUP_Pos [3/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 468 of file core_cm3.h.

◆ SCB_AIRCR_PRIGROUP_Pos [4/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 619 of file core_cm33.h.

◆ SCB_AIRCR_PRIGROUP_Pos [5/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 619 of file core_cm35p.h.

◆ SCB_AIRCR_PRIGROUP_Pos [6/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 526 of file core_cm4.h.

◆ SCB_AIRCR_PRIGROUP_Pos [7/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 570 of file core_cm7.h.

◆ SCB_AIRCR_PRIGROUP_Pos [8/8]

#define SCB_AIRCR_PRIGROUP_Pos 8U

SCB AIRCR: PRIGROUP Position

Definition at line 465 of file core_sc300.h.

◆ SCB_AIRCR_PRIS_Msk [1/6]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 623 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIS_Msk [2/6]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Msk [3/6]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 614 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Msk [4/6]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 471 of file core_cm23.h.

◆ SCB_AIRCR_PRIS_Msk [5/6]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 614 of file core_cm33.h.

◆ SCB_AIRCR_PRIS_Msk [6/6]

#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)

SCB AIRCR: PRIS Mask

Definition at line 614 of file core_cm35p.h.

◆ SCB_AIRCR_PRIS_Pos [1/6]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 622 of file core_armv81mml.h.

◆ SCB_AIRCR_PRIS_Pos [2/6]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 470 of file core_armv8mbl.h.

◆ SCB_AIRCR_PRIS_Pos [3/6]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 613 of file core_armv8mml.h.

◆ SCB_AIRCR_PRIS_Pos [4/6]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 470 of file core_cm23.h.

◆ SCB_AIRCR_PRIS_Pos [5/6]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 613 of file core_cm33.h.

◆ SCB_AIRCR_PRIS_Pos [6/6]

#define SCB_AIRCR_PRIS_Pos 14U

SCB AIRCR: PRIS Position

Definition at line 613 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [1/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 635 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [2/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [3/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 626 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [4/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [5/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 433 of file core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [6/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 409 of file core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [7/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 480 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [8/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 472 of file core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [9/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 626 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [10/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 626 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [11/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 530 of file core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [12/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 574 of file core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [13/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 421 of file core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Msk [14/14]

#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)

SCB AIRCR: SYSRESETREQ Mask

Definition at line 469 of file core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [1/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 634 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [2/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [3/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 625 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [4/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file core_cm0.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [5/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 432 of file core_cm0plus.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [6/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 408 of file core_cm1.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [7/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 479 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [8/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 471 of file core_cm3.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [9/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 625 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [10/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 625 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [11/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 529 of file core_cm4.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [12/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 573 of file core_cm7.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [13/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 420 of file core_sc000.h.

◆ SCB_AIRCR_SYSRESETREQ_Pos [14/14]

#define SCB_AIRCR_SYSRESETREQ_Pos 2U

SCB AIRCR: SYSRESETREQ Position

Definition at line 468 of file core_sc300.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [1/6]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 632 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [2/6]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [3/6]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 623 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [4/6]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 477 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [5/6]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 623 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Msk [6/6]

#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)

SCB AIRCR: SYSRESETREQS Mask

Definition at line 623 of file core_cm35p.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [1/6]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 631 of file core_armv81mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [2/6]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file core_armv8mbl.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [3/6]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 622 of file core_armv8mml.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [4/6]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 476 of file core_cm23.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [5/6]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 622 of file core_cm33.h.

◆ SCB_AIRCR_SYSRESETREQS_Pos [6/6]

#define SCB_AIRCR_SYSRESETREQS_Pos 3U

SCB AIRCR: SYSRESETREQS Position

Definition at line 622 of file core_cm35p.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [1/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 638 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [2/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [3/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 629 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [4/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [5/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 436 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [6/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 412 of file core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [7/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 483 of file core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [8/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 475 of file core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [9/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 629 of file core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [10/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 629 of file core_cm35p.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [11/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 533 of file core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [12/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 577 of file core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [13/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 424 of file core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Msk [14/14]

#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)

SCB AIRCR: VECTCLRACTIVE Mask

Definition at line 472 of file core_sc300.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [1/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 637 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [2/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [3/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 628 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [4/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file core_cm0.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [5/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 435 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [6/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 411 of file core_cm1.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [7/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 482 of file core_cm23.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [8/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 474 of file core_cm3.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [9/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 628 of file core_cm33.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [10/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 628 of file core_cm35p.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [11/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 532 of file core_cm4.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [12/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 576 of file core_cm7.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [13/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 423 of file core_sc000.h.

◆ SCB_AIRCR_VECTCLRACTIVE_Pos [14/14]

#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U

SCB AIRCR: VECTCLRACTIVE Position

Definition at line 471 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Msk [1/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 614 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [2/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Msk [3/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 605 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Msk [4/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Msk [5/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 424 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Msk [6/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 400 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Msk [7/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 462 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Msk [8/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 460 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Msk [9/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 605 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Msk [10/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 605 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEY_Msk [11/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 518 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Msk [12/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 562 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Msk [13/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 412 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Msk [14/14]

#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)

SCB AIRCR: VECTKEY Mask

Definition at line 457 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEY_Pos [1/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 613 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [2/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEY_Pos [3/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 604 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEY_Pos [4/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEY_Pos [5/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 423 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEY_Pos [6/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 399 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEY_Pos [7/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 461 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEY_Pos [8/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 459 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEY_Pos [9/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 604 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEY_Pos [10/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 604 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEY_Pos [11/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 517 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEY_Pos [12/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 561 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEY_Pos [13/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 411 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEY_Pos [14/14]

#define SCB_AIRCR_VECTKEY_Pos 16U

SCB AIRCR: VECTKEY Position

Definition at line 456 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [1/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 617 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [2/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [3/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 608 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [4/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [5/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 427 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [6/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 403 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [7/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 465 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [8/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 463 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [9/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 608 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [10/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 608 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [11/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 521 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [12/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 565 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [13/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 415 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Msk [14/14]

#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)

SCB AIRCR: VECTKEYSTAT Mask

Definition at line 460 of file core_sc300.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [1/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 616 of file core_armv81mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [2/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file core_armv8mbl.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [3/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 607 of file core_armv8mml.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [4/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file core_cm0.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [5/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 426 of file core_cm0plus.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [6/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 402 of file core_cm1.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [7/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 464 of file core_cm23.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [8/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 462 of file core_cm3.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [9/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 607 of file core_cm33.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [10/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 607 of file core_cm35p.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [11/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 520 of file core_cm4.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [12/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 564 of file core_cm7.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [13/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 414 of file core_sc000.h.

◆ SCB_AIRCR_VECTKEYSTAT_Pos [14/14]

#define SCB_AIRCR_VECTKEYSTAT_Pos 16U

SCB AIRCR: VECTKEYSTAT Position

Definition at line 459 of file core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Msk [1/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 478 of file core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Msk [2/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 536 of file core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Msk [3/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 580 of file core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Msk [4/4]

#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)

SCB AIRCR: VECTRESET Mask

Definition at line 475 of file core_sc300.h.

◆ SCB_AIRCR_VECTRESET_Pos [1/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 477 of file core_cm3.h.

◆ SCB_AIRCR_VECTRESET_Pos [2/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 535 of file core_cm4.h.

◆ SCB_AIRCR_VECTRESET_Pos [3/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 579 of file core_cm7.h.

◆ SCB_AIRCR_VECTRESET_Pos [4/4]

#define SCB_AIRCR_VECTRESET_Pos 0U

SCB AIRCR: VECTRESET Position

Definition at line 474 of file core_sc300.h.

◆ SCB_BASE [1/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 2041 of file core_armv81mml.h.

◆ SCB_BASE [2/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1119 of file core_armv8mbl.h.

◆ SCB_BASE [3/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1885 of file core_armv8mml.h.

◆ SCB_BASE [4/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 537 of file core_cm0.h.

◆ SCB_BASE [5/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 651 of file core_cm0plus.h.

◆ SCB_BASE [6/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 563 of file core_cm1.h.

◆ SCB_BASE [7/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1194 of file core_cm23.h.

◆ SCB_BASE [8/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1382 of file core_cm3.h.

◆ SCB_BASE [9/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1960 of file core_cm33.h.

◆ SCB_BASE [10/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1960 of file core_cm35p.h.

◆ SCB_BASE [11/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1552 of file core_cm4.h.

◆ SCB_BASE [12/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1775 of file core_cm7.h.

◆ SCB_BASE [13/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 660 of file core_sc000.h.

◆ SCB_BASE [14/14]

#define SCB_BASE (SCS_BASE + 0x0D00UL)

System Control Block Base Address

Definition at line 1365 of file core_sc300.h.

◆ SCB_CACR_ECCEN_Msk [1/2]

#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 963 of file core_armv81mml.h.

◆ SCB_CACR_ECCEN_Msk [2/2]

#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)

SCB CACR: ECCEN Mask

Definition at line 874 of file core_cm7.h.

◆ SCB_CACR_ECCEN_Pos [1/2]

#define SCB_CACR_ECCEN_Pos 1U

SCB CACR: ECCEN Position

Definition at line 962 of file core_armv81mml.h.

◆ SCB_CACR_ECCEN_Pos [2/2]

#define SCB_CACR_ECCEN_Pos 1U

SCB CACR: ECCEN Position

Definition at line 873 of file core_cm7.h.

◆ SCB_CACR_FORCEWT_Msk [1/2]

#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 960 of file core_armv81mml.h.

◆ SCB_CACR_FORCEWT_Msk [2/2]

#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)

SCB CACR: FORCEWT Mask

Definition at line 871 of file core_cm7.h.

◆ SCB_CACR_FORCEWT_Pos [1/2]

#define SCB_CACR_FORCEWT_Pos 2U

SCB CACR: FORCEWT Position

Definition at line 959 of file core_armv81mml.h.

◆ SCB_CACR_FORCEWT_Pos [2/2]

#define SCB_CACR_FORCEWT_Pos 2U

SCB CACR: FORCEWT Position

Definition at line 870 of file core_cm7.h.

◆ SCB_CACR_SIWT_Msk [1/2]

#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 966 of file core_armv81mml.h.

◆ SCB_CACR_SIWT_Msk [2/2]

#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)

SCB CACR: SIWT Mask

Definition at line 877 of file core_cm7.h.

◆ SCB_CACR_SIWT_Pos [1/2]

#define SCB_CACR_SIWT_Pos 0U

SCB CACR: SIWT Position

Definition at line 965 of file core_armv81mml.h.

◆ SCB_CACR_SIWT_Pos [2/2]

#define SCB_CACR_SIWT_Pos 0U

SCB CACR: SIWT Position

Definition at line 876 of file core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [1/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 667 of file core_armv81mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [2/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Msk [3/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 658 of file core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Msk [4/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 512 of file core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Msk [5/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 495 of file core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Msk [6/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 658 of file core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Msk [7/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 658 of file core_cm35p.h.

◆ SCB_CCR_BFHFNMIGN_Msk [8/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 553 of file core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Msk [9/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 606 of file core_cm7.h.

◆ SCB_CCR_BFHFNMIGN_Msk [10/10]

#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)

SCB CCR: BFHFNMIGN Mask

Definition at line 492 of file core_sc300.h.

◆ SCB_CCR_BFHFNMIGN_Pos [1/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 666 of file core_armv81mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [2/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file core_armv8mbl.h.

◆ SCB_CCR_BFHFNMIGN_Pos [3/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 657 of file core_armv8mml.h.

◆ SCB_CCR_BFHFNMIGN_Pos [4/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 511 of file core_cm23.h.

◆ SCB_CCR_BFHFNMIGN_Pos [5/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 494 of file core_cm3.h.

◆ SCB_CCR_BFHFNMIGN_Pos [6/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 657 of file core_cm33.h.

◆ SCB_CCR_BFHFNMIGN_Pos [7/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 657 of file core_cm35p.h.

◆ SCB_CCR_BFHFNMIGN_Pos [8/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 552 of file core_cm4.h.

◆ SCB_CCR_BFHFNMIGN_Pos [9/10]

#define SCB_CCR_BFHFNMIGN_Pos 8U

SCB CCR: BFHFNMIGN Position

Definition at line 605 of file core_cm7.h.

#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)

SCB CCR: BP Mask

SCB CCR: Branch prediction enable bit Mask

Definition at line 646 of file core_cm35p.h.

#define SCB_CCR_BP_Pos 18U

SCB CCR: BP Position

SCB CCR: Branch prediction enable bit Position

Definition at line 645 of file core_cm35p.h.

SCB CCR: IC Position

SCB CCR: Instruction cache enable bit Position

Definition at line 648 of file core_cm35p.h.

◆ SCB_CCR_IC_Pos [7/7]

#define SCB_CCR_IC_Pos 17U

SCB CCR: Instruction cache enable bit Position

Definition at line 596 of file core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [1/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 507 of file core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [2/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 565 of file core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [3/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 618 of file core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Msk [4/4]

#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)

SCB CCR: NONBASETHRDENA Mask

Definition at line 504 of file core_sc300.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [1/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 506 of file core_cm3.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [2/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 564 of file core_cm4.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [3/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 617 of file core_cm7.h.

◆ SCB_CCR_NONBASETHRDENA_Pos [4/4]

#define SCB_CCR_NONBASETHRDENA_Pos 0U

SCB CCR: NONBASETHRDENA Position

Definition at line 503 of file core_sc300.h.

◆ SCB_CCR_STKALIGN_Msk [1/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file core_cm0.h.

◆ SCB_CCR_STKALIGN_Msk [2/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 450 of file core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Msk [3/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 426 of file core_cm1.h.

◆ SCB_CCR_STKALIGN_Msk [4/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 492 of file core_cm3.h.

◆ SCB_CCR_STKALIGN_Msk [5/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 550 of file core_cm4.h.

◆ SCB_CCR_STKALIGN_Msk [6/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 603 of file core_cm7.h.

◆ SCB_CCR_STKALIGN_Msk [7/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 438 of file core_sc000.h.

◆ SCB_CCR_STKALIGN_Msk [8/8]

#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)

SCB CCR: STKALIGN Mask

Definition at line 489 of file core_sc300.h.

◆ SCB_CCR_STKALIGN_Pos [1/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 425 of file core_cm0.h.

◆ SCB_CCR_STKALIGN_Pos [2/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 449 of file core_cm0plus.h.

◆ SCB_CCR_STKALIGN_Pos [3/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 425 of file core_cm1.h.

◆ SCB_CCR_STKALIGN_Pos [4/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 491 of file core_cm3.h.

◆ SCB_CCR_STKALIGN_Pos [5/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 549 of file core_cm4.h.

◆ SCB_CCR_STKALIGN_Pos [6/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 602 of file core_cm7.h.

◆ SCB_CCR_STKALIGN_Pos [7/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 437 of file core_sc000.h.

◆ SCB_CCR_STKALIGN_Pos [8/8]

#define SCB_CCR_STKALIGN_Pos 9U

SCB CCR: STKALIGN Position

Definition at line 488 of file core_sc300.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [1/6]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 664 of file core_armv81mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [2/6]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [3/6]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 655 of file core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [4/6]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 509 of file core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [5/6]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 655 of file core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Msk [6/6]

#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)

SCB CCR: STKOFHFNMIGN Mask

Definition at line 655 of file core_cm35p.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [1/6]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 663 of file core_armv81mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [2/6]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file core_armv8mbl.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [3/6]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 654 of file core_armv8mml.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [4/6]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 508 of file core_cm23.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [5/6]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 654 of file core_cm33.h.

◆ SCB_CCR_STKOFHFNMIGN_Pos [6/6]

#define SCB_CCR_STKOFHFNMIGN_Pos 10U

SCB CCR: STKOFHFNMIGN Position

Definition at line 654 of file core_cm35p.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [1/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 673 of file core_armv81mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [2/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [3/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 664 of file core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [4/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [5/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 453 of file core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [6/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 429 of file core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [7/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 518 of file core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [8/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 501 of file core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [9/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 664 of file core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [10/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 664 of file core_cm35p.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [11/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 559 of file core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [12/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 612 of file core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [13/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 441 of file core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Msk [14/14]

#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)

SCB CCR: UNALIGN_TRP Mask

Definition at line 498 of file core_sc300.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [1/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 672 of file core_armv81mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [2/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file core_armv8mbl.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [3/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 663 of file core_armv8mml.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [4/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file core_cm0.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [5/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 452 of file core_cm0plus.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [6/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 428 of file core_cm1.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [7/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 517 of file core_cm23.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [8/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 500 of file core_cm3.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [9/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 663 of file core_cm33.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [10/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 663 of file core_cm35p.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [11/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 558 of file core_cm4.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [12/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 611 of file core_cm7.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [13/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 440 of file core_sc000.h.

◆ SCB_CCR_UNALIGN_TRP_Pos [14/14]

#define SCB_CCR_UNALIGN_TRP_Pos 3U

SCB CCR: UNALIGN_TRP Position

Definition at line 497 of file core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Msk [1/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 676 of file core_armv81mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [2/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Msk [3/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 667 of file core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Msk [4/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 521 of file core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Msk [5/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 504 of file core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Msk [6/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 667 of file core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Msk [7/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 667 of file core_cm35p.h.

◆ SCB_CCR_USERSETMPEND_Msk [8/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 562 of file core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Msk [9/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 615 of file core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Msk [10/10]

#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)

SCB CCR: USERSETMPEND Mask

Definition at line 501 of file core_sc300.h.

◆ SCB_CCR_USERSETMPEND_Pos [1/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 675 of file core_armv81mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [2/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file core_armv8mbl.h.

◆ SCB_CCR_USERSETMPEND_Pos [3/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 666 of file core_armv8mml.h.

◆ SCB_CCR_USERSETMPEND_Pos [4/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 520 of file core_cm23.h.

◆ SCB_CCR_USERSETMPEND_Pos [5/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 503 of file core_cm3.h.

◆ SCB_CCR_USERSETMPEND_Pos [6/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 666 of file core_cm33.h.

◆ SCB_CCR_USERSETMPEND_Pos [7/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 666 of file core_cm35p.h.

◆ SCB_CCR_USERSETMPEND_Pos [8/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 561 of file core_cm4.h.

◆ SCB_CCR_USERSETMPEND_Pos [9/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 614 of file core_cm7.h.

◆ SCB_CCR_USERSETMPEND_Pos [10/10]

#define SCB_CCR_USERSETMPEND_Pos 1U

SCB CCR: USERSETMPEND Position

Definition at line 500 of file core_sc300.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [1/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 888 of file core_armv81mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [2/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 879 of file core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [3/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 879 of file core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [4/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 879 of file core_cm35p.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Msk [5/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)

SCB CCSIDR: Associativity Mask

Definition at line 799 of file core_cm7.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [1/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 887 of file core_armv81mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [2/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 878 of file core_armv8mml.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [3/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 878 of file core_cm33.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [4/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 878 of file core_cm35p.h.

◆ SCB_CCSIDR_ASSOCIATIVITY_Pos [5/5]

#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U

SCB CCSIDR: Associativity Position

Definition at line 798 of file core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Msk [1/5]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 891 of file core_armv81mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [2/5]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 882 of file core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Msk [3/5]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 882 of file core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Msk [4/5]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 882 of file core_cm35p.h.

◆ SCB_CCSIDR_LINESIZE_Msk [5/5]

#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)

SCB CCSIDR: LineSize Mask

Definition at line 802 of file core_cm7.h.

◆ SCB_CCSIDR_LINESIZE_Pos [1/5]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 890 of file core_armv81mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [2/5]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 881 of file core_armv8mml.h.

◆ SCB_CCSIDR_LINESIZE_Pos [3/5]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 881 of file core_cm33.h.

◆ SCB_CCSIDR_LINESIZE_Pos [4/5]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 881 of file core_cm35p.h.

◆ SCB_CCSIDR_LINESIZE_Pos [5/5]

#define SCB_CCSIDR_LINESIZE_Pos 0U

SCB CCSIDR: LineSize Position

Definition at line 801 of file core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Msk [1/5]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 885 of file core_armv81mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [2/5]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 876 of file core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Msk [3/5]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 876 of file core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Msk [4/5]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 876 of file core_cm35p.h.

◆ SCB_CCSIDR_NUMSETS_Msk [5/5]

#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)

SCB CCSIDR: NumSets Mask

Definition at line 796 of file core_cm7.h.

◆ SCB_CCSIDR_NUMSETS_Pos [1/5]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 884 of file core_armv81mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [2/5]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 875 of file core_armv8mml.h.

◆ SCB_CCSIDR_NUMSETS_Pos [3/5]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 875 of file core_cm33.h.

◆ SCB_CCSIDR_NUMSETS_Pos [4/5]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 875 of file core_cm35p.h.

◆ SCB_CCSIDR_NUMSETS_Pos [5/5]

#define SCB_CCSIDR_NUMSETS_Pos 13U

SCB CCSIDR: NumSets Position

Definition at line 795 of file core_cm7.h.

◆ SCB_CCSIDR_RA_Msk [1/5]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 879 of file core_armv81mml.h.

◆ SCB_CCSIDR_RA_Msk [2/5]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 870 of file core_armv8mml.h.

◆ SCB_CCSIDR_RA_Msk [3/5]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 870 of file core_cm33.h.

◆ SCB_CCSIDR_RA_Msk [4/5]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 870 of file core_cm35p.h.

◆ SCB_CCSIDR_RA_Msk [5/5]

#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)

SCB CCSIDR: RA Mask

Definition at line 790 of file core_cm7.h.

◆ SCB_CCSIDR_RA_Pos [1/5]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 878 of file core_armv81mml.h.

◆ SCB_CCSIDR_RA_Pos [2/5]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 869 of file core_armv8mml.h.

◆ SCB_CCSIDR_RA_Pos [3/5]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 869 of file core_cm33.h.

◆ SCB_CCSIDR_RA_Pos [4/5]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 869 of file core_cm35p.h.

◆ SCB_CCSIDR_RA_Pos [5/5]

#define SCB_CCSIDR_RA_Pos 29U

SCB CCSIDR: RA Position

Definition at line 789 of file core_cm7.h.

◆ SCB_CCSIDR_WA_Msk [1/5]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 882 of file core_armv81mml.h.

◆ SCB_CCSIDR_WA_Msk [2/5]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 873 of file core_armv8mml.h.

◆ SCB_CCSIDR_WA_Msk [3/5]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 873 of file core_cm33.h.

◆ SCB_CCSIDR_WA_Msk [4/5]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 873 of file core_cm35p.h.

◆ SCB_CCSIDR_WA_Msk [5/5]

#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)

SCB CCSIDR: WA Mask

Definition at line 793 of file core_cm7.h.

◆ SCB_CCSIDR_WA_Pos [1/5]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 881 of file core_armv81mml.h.

◆ SCB_CCSIDR_WA_Pos [2/5]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 872 of file core_armv8mml.h.

◆ SCB_CCSIDR_WA_Pos [3/5]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 872 of file core_cm33.h.

◆ SCB_CCSIDR_WA_Pos [4/5]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 872 of file core_cm35p.h.

◆ SCB_CCSIDR_WA_Pos [5/5]

#define SCB_CCSIDR_WA_Pos 28U

SCB CCSIDR: WA Position

Definition at line 792 of file core_cm7.h.

◆ SCB_CCSIDR_WB_Msk [1/5]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 876 of file core_armv81mml.h.

◆ SCB_CCSIDR_WB_Msk [2/5]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 867 of file core_armv8mml.h.

◆ SCB_CCSIDR_WB_Msk [3/5]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 867 of file core_cm33.h.

◆ SCB_CCSIDR_WB_Msk [4/5]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 867 of file core_cm35p.h.

◆ SCB_CCSIDR_WB_Msk [5/5]

#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)

SCB CCSIDR: WB Mask

Definition at line 787 of file core_cm7.h.

◆ SCB_CCSIDR_WB_Pos [1/5]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 875 of file core_armv81mml.h.

◆ SCB_CCSIDR_WB_Pos [2/5]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 866 of file core_armv8mml.h.

◆ SCB_CCSIDR_WB_Pos [3/5]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 866 of file core_cm33.h.

◆ SCB_CCSIDR_WB_Pos [4/5]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 866 of file core_cm35p.h.

◆ SCB_CCSIDR_WB_Pos [5/5]

#define SCB_CCSIDR_WB_Pos 30U

SCB CCSIDR: WB Position

Definition at line 786 of file core_cm7.h.

◆ SCB_CCSIDR_WT_Msk [1/5]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 873 of file core_armv81mml.h.

◆ SCB_CCSIDR_WT_Msk [2/5]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 864 of file core_armv8mml.h.

◆ SCB_CCSIDR_WT_Msk [3/5]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 864 of file core_cm33.h.

◆ SCB_CCSIDR_WT_Msk [4/5]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 864 of file core_cm35p.h.

◆ SCB_CCSIDR_WT_Msk [5/5]

#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)

SCB CCSIDR: WT Mask

Definition at line 784 of file core_cm7.h.

◆ SCB_CCSIDR_WT_Pos [1/5]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 872 of file core_armv81mml.h.

◆ SCB_CCSIDR_WT_Pos [2/5]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 863 of file core_armv8mml.h.

◆ SCB_CCSIDR_WT_Pos [3/5]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 863 of file core_cm33.h.

◆ SCB_CCSIDR_WT_Pos [4/5]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 863 of file core_cm35p.h.

◆ SCB_CCSIDR_WT_Pos [5/5]

#define SCB_CCSIDR_WT_Pos 31U

SCB CCSIDR: WT Position

Definition at line 783 of file core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [1/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 770 of file core_armv81mml.h.

◆ SCB_CFSR_BFARVALID_Msk [2/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 761 of file core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Msk [3/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 580 of file core_cm3.h.

◆ SCB_CFSR_BFARVALID_Msk [4/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 761 of file core_cm33.h.

◆ SCB_CFSR_BFARVALID_Msk [5/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 761 of file core_cm35p.h.

◆ SCB_CFSR_BFARVALID_Msk [6/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 641 of file core_cm4.h.

◆ SCB_CFSR_BFARVALID_Msk [7/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 694 of file core_cm7.h.

◆ SCB_CFSR_BFARVALID_Msk [8/8]

#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

Definition at line 577 of file core_sc300.h.

◆ SCB_CFSR_BFARVALID_Pos [1/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 769 of file core_armv81mml.h.

◆ SCB_CFSR_BFARVALID_Pos [2/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 760 of file core_armv8mml.h.

◆ SCB_CFSR_BFARVALID_Pos [3/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 579 of file core_cm3.h.

◆ SCB_CFSR_BFARVALID_Pos [4/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 760 of file core_cm33.h.

◆ SCB_CFSR_BFARVALID_Pos [5/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 760 of file core_cm35p.h.

◆ SCB_CFSR_BFARVALID_Pos [6/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 640 of file core_cm4.h.

◆ SCB_CFSR_BFARVALID_Pos [7/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 693 of file core_cm7.h.

◆ SCB_CFSR_BFARVALID_Pos [8/8]

#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

Definition at line 576 of file core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [1/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 744 of file core_armv81mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [2/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 735 of file core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [3/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 557 of file core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [4/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 735 of file core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [5/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 735 of file core_cm35p.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [6/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 615 of file core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [7/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 668 of file core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Msk [8/8]

#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)

SCB CFSR: Bus Fault Status Register Mask

Definition at line 554 of file core_sc300.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [1/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 743 of file core_armv81mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [2/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 734 of file core_armv8mml.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [3/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 556 of file core_cm3.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [4/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 734 of file core_cm33.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [5/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 734 of file core_cm35p.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [6/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 614 of file core_cm4.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [7/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 667 of file core_cm7.h.

◆ SCB_CFSR_BUSFAULTSR_Pos [8/8]

#define SCB_CFSR_BUSFAULTSR_Pos 8U

SCB CFSR: Bus Fault Status Register Position

Definition at line 553 of file core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Msk [1/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 763 of file core_armv81mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [2/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 754 of file core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Msk [3/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 573 of file core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Msk [4/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 754 of file core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Msk [5/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 754 of file core_cm35p.h.

◆ SCB_CFSR_DACCVIOL_Msk [6/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 634 of file core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Msk [7/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 687 of file core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Msk [8/8]

#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

Definition at line 570 of file core_sc300.h.

◆ SCB_CFSR_DACCVIOL_Pos [1/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 762 of file core_armv81mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [2/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 753 of file core_armv8mml.h.

◆ SCB_CFSR_DACCVIOL_Pos [3/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 572 of file core_cm3.h.

◆ SCB_CFSR_DACCVIOL_Pos [4/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 753 of file core_cm33.h.

◆ SCB_CFSR_DACCVIOL_Pos [5/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 753 of file core_cm35p.h.

◆ SCB_CFSR_DACCVIOL_Pos [6/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 633 of file core_cm4.h.

◆ SCB_CFSR_DACCVIOL_Pos [7/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 686 of file core_cm7.h.

◆ SCB_CFSR_DACCVIOL_Pos [8/8]

#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

Definition at line 569 of file core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Msk [1/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 792 of file core_armv81mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [2/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 783 of file core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Msk [3/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 599 of file core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Msk [4/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 783 of file core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Msk [5/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 783 of file core_cm35p.h.

◆ SCB_CFSR_DIVBYZERO_Msk [6/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 663 of file core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Msk [7/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 716 of file core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Msk [8/8]

#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

Definition at line 596 of file core_sc300.h.

◆ SCB_CFSR_DIVBYZERO_Pos [1/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 791 of file core_armv81mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [2/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 782 of file core_armv8mml.h.

◆ SCB_CFSR_DIVBYZERO_Pos [3/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 598 of file core_cm3.h.

◆ SCB_CFSR_DIVBYZERO_Pos [4/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 782 of file core_cm33.h.

◆ SCB_CFSR_DIVBYZERO_Pos [5/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 782 of file core_cm35p.h.

◆ SCB_CFSR_DIVBYZERO_Pos [6/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 662 of file core_cm4.h.

◆ SCB_CFSR_DIVBYZERO_Pos [7/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 715 of file core_cm7.h.

◆ SCB_CFSR_DIVBYZERO_Pos [8/8]

#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

Definition at line 595 of file core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Msk [1/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 766 of file core_armv81mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [2/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 757 of file core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Msk [3/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 576 of file core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Msk [4/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 757 of file core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Msk [5/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 757 of file core_cm35p.h.

◆ SCB_CFSR_IACCVIOL_Msk [6/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 637 of file core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Msk [7/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 690 of file core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Msk [8/8]

#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

Definition at line 573 of file core_sc300.h.

◆ SCB_CFSR_IACCVIOL_Pos [1/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 765 of file core_armv81mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [2/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 756 of file core_armv8mml.h.

◆ SCB_CFSR_IACCVIOL_Pos [3/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 575 of file core_cm3.h.

◆ SCB_CFSR_IACCVIOL_Pos [4/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 756 of file core_cm33.h.

◆ SCB_CFSR_IACCVIOL_Pos [5/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 756 of file core_cm35p.h.

◆ SCB_CFSR_IACCVIOL_Pos [6/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 636 of file core_cm4.h.

◆ SCB_CFSR_IACCVIOL_Pos [7/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 689 of file core_cm7.h.

◆ SCB_CFSR_IACCVIOL_Pos [8/8]

#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

SCB CFSR (MMFSR): IACCVIOL Position

Definition at line 572 of file core_sc300.h.

◆ SCB_CFSR_IBUSERR_Msk [1/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 788 of file core_armv81mml.h.

◆ SCB_CFSR_IBUSERR_Msk [2/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 779 of file core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Msk [3/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 595 of file core_cm3.h.

◆ SCB_CFSR_IBUSERR_Msk [4/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 779 of file core_cm33.h.

◆ SCB_CFSR_IBUSERR_Msk [5/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 779 of file core_cm35p.h.

◆ SCB_CFSR_IBUSERR_Msk [6/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 659 of file core_cm4.h.

◆ SCB_CFSR_IBUSERR_Msk [7/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 712 of file core_cm7.h.

◆ SCB_CFSR_IBUSERR_Msk [8/8]

#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

Definition at line 592 of file core_sc300.h.

◆ SCB_CFSR_IBUSERR_Pos [1/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 787 of file core_armv81mml.h.

◆ SCB_CFSR_IBUSERR_Pos [2/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 778 of file core_armv8mml.h.

◆ SCB_CFSR_IBUSERR_Pos [3/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 594 of file core_cm3.h.

◆ SCB_CFSR_IBUSERR_Pos [4/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 778 of file core_cm33.h.

◆ SCB_CFSR_IBUSERR_Pos [5/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 778 of file core_cm35p.h.

◆ SCB_CFSR_IBUSERR_Pos [6/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 658 of file core_cm4.h.

◆ SCB_CFSR_IBUSERR_Pos [7/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 711 of file core_cm7.h.

◆ SCB_CFSR_IBUSERR_Pos [8/8]

#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

Definition at line 591 of file core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Msk [1/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 782 of file core_armv81mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [2/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 773 of file core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Msk [3/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 589 of file core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Msk [4/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 773 of file core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Msk [5/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 773 of file core_cm35p.h.

◆ SCB_CFSR_IMPRECISERR_Msk [6/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 653 of file core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Msk [7/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 706 of file core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Msk [8/8]

#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

Definition at line 586 of file core_sc300.h.

◆ SCB_CFSR_IMPRECISERR_Pos [1/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 781 of file core_armv81mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [2/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 772 of file core_armv8mml.h.

◆ SCB_CFSR_IMPRECISERR_Pos [3/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 588 of file core_cm3.h.

◆ SCB_CFSR_IMPRECISERR_Pos [4/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 772 of file core_cm33.h.

◆ SCB_CFSR_IMPRECISERR_Pos [5/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 772 of file core_cm35p.h.

◆ SCB_CFSR_IMPRECISERR_Pos [6/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 652 of file core_cm4.h.

◆ SCB_CFSR_IMPRECISERR_Pos [7/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 705 of file core_cm7.h.

◆ SCB_CFSR_IMPRECISERR_Pos [8/8]

#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

Definition at line 585 of file core_sc300.h.

◆ SCB_CFSR_INVPC_Msk [1/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 804 of file core_armv81mml.h.

◆ SCB_CFSR_INVPC_Msk [2/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 795 of file core_armv8mml.h.

◆ SCB_CFSR_INVPC_Msk [3/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 608 of file core_cm3.h.

◆ SCB_CFSR_INVPC_Msk [4/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 795 of file core_cm33.h.

◆ SCB_CFSR_INVPC_Msk [5/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 795 of file core_cm35p.h.

◆ SCB_CFSR_INVPC_Msk [6/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 672 of file core_cm4.h.

◆ SCB_CFSR_INVPC_Msk [7/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 725 of file core_cm7.h.

◆ SCB_CFSR_INVPC_Msk [8/8]

#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

Definition at line 605 of file core_sc300.h.

◆ SCB_CFSR_INVPC_Pos [1/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 803 of file core_armv81mml.h.

◆ SCB_CFSR_INVPC_Pos [2/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 794 of file core_armv8mml.h.

◆ SCB_CFSR_INVPC_Pos [3/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 607 of file core_cm3.h.

◆ SCB_CFSR_INVPC_Pos [4/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 794 of file core_cm33.h.

◆ SCB_CFSR_INVPC_Pos [5/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 794 of file core_cm35p.h.

◆ SCB_CFSR_INVPC_Pos [6/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 671 of file core_cm4.h.

◆ SCB_CFSR_INVPC_Pos [7/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 724 of file core_cm7.h.

◆ SCB_CFSR_INVPC_Pos [8/8]

#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

Definition at line 604 of file core_sc300.h.

◆ SCB_CFSR_INVSTATE_Msk [1/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 807 of file core_armv81mml.h.

◆ SCB_CFSR_INVSTATE_Msk [2/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 798 of file core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Msk [3/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 611 of file core_cm3.h.

◆ SCB_CFSR_INVSTATE_Msk [4/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 798 of file core_cm33.h.

◆ SCB_CFSR_INVSTATE_Msk [5/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 798 of file core_cm35p.h.

◆ SCB_CFSR_INVSTATE_Msk [6/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 675 of file core_cm4.h.

◆ SCB_CFSR_INVSTATE_Msk [7/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 728 of file core_cm7.h.

◆ SCB_CFSR_INVSTATE_Msk [8/8]

#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

Definition at line 608 of file core_sc300.h.

◆ SCB_CFSR_INVSTATE_Pos [1/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 806 of file core_armv81mml.h.

◆ SCB_CFSR_INVSTATE_Pos [2/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 797 of file core_armv8mml.h.

◆ SCB_CFSR_INVSTATE_Pos [3/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 610 of file core_cm3.h.

◆ SCB_CFSR_INVSTATE_Pos [4/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 797 of file core_cm33.h.

◆ SCB_CFSR_INVSTATE_Pos [5/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 797 of file core_cm35p.h.

◆ SCB_CFSR_INVSTATE_Pos [6/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 674 of file core_cm4.h.

◆ SCB_CFSR_INVSTATE_Pos [7/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 727 of file core_cm7.h.

◆ SCB_CFSR_INVSTATE_Pos [8/8]

#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

Definition at line 607 of file core_sc300.h.

◆ SCB_CFSR_LSPERR_Msk [1/6]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 773 of file core_armv81mml.h.

◆ SCB_CFSR_LSPERR_Msk [2/6]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 764 of file core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Msk [3/6]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 764 of file core_cm33.h.

◆ SCB_CFSR_LSPERR_Msk [4/6]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 764 of file core_cm35p.h.

◆ SCB_CFSR_LSPERR_Msk [5/6]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 644 of file core_cm4.h.

◆ SCB_CFSR_LSPERR_Msk [6/6]

#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)

SCB CFSR (BFSR): LSPERR Mask

Definition at line 697 of file core_cm7.h.

◆ SCB_CFSR_LSPERR_Pos [1/6]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 772 of file core_armv81mml.h.

◆ SCB_CFSR_LSPERR_Pos [2/6]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 763 of file core_armv8mml.h.

◆ SCB_CFSR_LSPERR_Pos [3/6]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 763 of file core_cm33.h.

◆ SCB_CFSR_LSPERR_Pos [4/6]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 763 of file core_cm35p.h.

◆ SCB_CFSR_LSPERR_Pos [5/6]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 643 of file core_cm4.h.

◆ SCB_CFSR_LSPERR_Pos [6/6]

#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)

SCB CFSR (BFSR): LSPERR Position

Definition at line 696 of file core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [1/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 747 of file core_armv81mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [2/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 738 of file core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [3/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 560 of file core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [4/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 738 of file core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [5/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 738 of file core_cm35p.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [6/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 618 of file core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [7/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 671 of file core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Msk [8/8]

#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)

SCB CFSR: Memory Manage Fault Status Register Mask

Definition at line 557 of file core_sc300.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [1/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 746 of file core_armv81mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [2/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 737 of file core_armv8mml.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [3/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 559 of file core_cm3.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [4/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 737 of file core_cm33.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [5/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 737 of file core_cm35p.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [6/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 617 of file core_cm4.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [7/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 670 of file core_cm7.h.

◆ SCB_CFSR_MEMFAULTSR_Pos [8/8]

#define SCB_CFSR_MEMFAULTSR_Pos 0U

SCB CFSR: Memory Manage Fault Status Register Position

Definition at line 556 of file core_sc300.h.

◆ SCB_CFSR_MLSPERR_Msk [1/6]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 754 of file core_armv81mml.h.

◆ SCB_CFSR_MLSPERR_Msk [2/6]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 745 of file core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Msk [3/6]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 745 of file core_cm33.h.

◆ SCB_CFSR_MLSPERR_Msk [4/6]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 745 of file core_cm35p.h.

◆ SCB_CFSR_MLSPERR_Msk [5/6]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 625 of file core_cm4.h.

◆ SCB_CFSR_MLSPERR_Msk [6/6]

#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)

SCB CFSR (MMFSR): MLSPERR Mask

Definition at line 678 of file core_cm7.h.

◆ SCB_CFSR_MLSPERR_Pos [1/6]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 753 of file core_armv81mml.h.

◆ SCB_CFSR_MLSPERR_Pos [2/6]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 744 of file core_armv8mml.h.

◆ SCB_CFSR_MLSPERR_Pos [3/6]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 744 of file core_cm33.h.

◆ SCB_CFSR_MLSPERR_Pos [4/6]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 744 of file core_cm35p.h.

◆ SCB_CFSR_MLSPERR_Pos [5/6]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 624 of file core_cm4.h.

◆ SCB_CFSR_MLSPERR_Pos [6/6]

#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)

SCB CFSR (MMFSR): MLSPERR Position

Definition at line 677 of file core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [1/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 751 of file core_armv81mml.h.

◆ SCB_CFSR_MMARVALID_Msk [2/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 742 of file core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Msk [3/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 564 of file core_cm3.h.

◆ SCB_CFSR_MMARVALID_Msk [4/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 742 of file core_cm33.h.

◆ SCB_CFSR_MMARVALID_Msk [5/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 742 of file core_cm35p.h.

◆ SCB_CFSR_MMARVALID_Msk [6/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 622 of file core_cm4.h.

◆ SCB_CFSR_MMARVALID_Msk [7/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 675 of file core_cm7.h.

◆ SCB_CFSR_MMARVALID_Msk [8/8]

#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

Definition at line 561 of file core_sc300.h.

◆ SCB_CFSR_MMARVALID_Pos [1/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 750 of file core_armv81mml.h.

◆ SCB_CFSR_MMARVALID_Pos [2/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 741 of file core_armv8mml.h.

◆ SCB_CFSR_MMARVALID_Pos [3/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 563 of file core_cm3.h.

◆ SCB_CFSR_MMARVALID_Pos [4/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 741 of file core_cm33.h.

◆ SCB_CFSR_MMARVALID_Pos [5/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 741 of file core_cm35p.h.

◆ SCB_CFSR_MMARVALID_Pos [6/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 621 of file core_cm4.h.

◆ SCB_CFSR_MMARVALID_Pos [7/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 674 of file core_cm7.h.

◆ SCB_CFSR_MMARVALID_Pos [8/8]

#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

Definition at line 560 of file core_sc300.h.

◆ SCB_CFSR_MSTKERR_Msk [1/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 757 of file core_armv81mml.h.

◆ SCB_CFSR_MSTKERR_Msk [2/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 748 of file core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Msk [3/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 567 of file core_cm3.h.

◆ SCB_CFSR_MSTKERR_Msk [4/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 748 of file core_cm33.h.

◆ SCB_CFSR_MSTKERR_Msk [5/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 748 of file core_cm35p.h.

◆ SCB_CFSR_MSTKERR_Msk [6/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 628 of file core_cm4.h.

◆ SCB_CFSR_MSTKERR_Msk [7/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 681 of file core_cm7.h.

◆ SCB_CFSR_MSTKERR_Msk [8/8]

#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

Definition at line 564 of file core_sc300.h.

◆ SCB_CFSR_MSTKERR_Pos [1/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 756 of file core_armv81mml.h.

◆ SCB_CFSR_MSTKERR_Pos [2/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 747 of file core_armv8mml.h.

◆ SCB_CFSR_MSTKERR_Pos [3/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 566 of file core_cm3.h.

◆ SCB_CFSR_MSTKERR_Pos [4/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 747 of file core_cm33.h.

◆ SCB_CFSR_MSTKERR_Pos [5/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 747 of file core_cm35p.h.

◆ SCB_CFSR_MSTKERR_Pos [6/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 627 of file core_cm4.h.

◆ SCB_CFSR_MSTKERR_Pos [7/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 680 of file core_cm7.h.

◆ SCB_CFSR_MSTKERR_Pos [8/8]

#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

Definition at line 563 of file core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Msk [1/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 760 of file core_armv81mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [2/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 751 of file core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Msk [3/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 570 of file core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Msk [4/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 751 of file core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Msk [5/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 751 of file core_cm35p.h.

◆ SCB_CFSR_MUNSTKERR_Msk [6/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 631 of file core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Msk [7/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 684 of file core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Msk [8/8]

#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

Definition at line 567 of file core_sc300.h.

◆ SCB_CFSR_MUNSTKERR_Pos [1/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 759 of file core_armv81mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [2/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 750 of file core_armv8mml.h.

◆ SCB_CFSR_MUNSTKERR_Pos [3/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 569 of file core_cm3.h.

◆ SCB_CFSR_MUNSTKERR_Pos [4/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 750 of file core_cm33.h.

◆ SCB_CFSR_MUNSTKERR_Pos [5/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 750 of file core_cm35p.h.

◆ SCB_CFSR_MUNSTKERR_Pos [6/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 630 of file core_cm4.h.

◆ SCB_CFSR_MUNSTKERR_Pos [7/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 683 of file core_cm7.h.

◆ SCB_CFSR_MUNSTKERR_Pos [8/8]

#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

Definition at line 566 of file core_sc300.h.

◆ SCB_CFSR_NOCP_Msk [1/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 801 of file core_armv81mml.h.

◆ SCB_CFSR_NOCP_Msk [2/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 792 of file core_armv8mml.h.

◆ SCB_CFSR_NOCP_Msk [3/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 605 of file core_cm3.h.

◆ SCB_CFSR_NOCP_Msk [4/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 792 of file core_cm33.h.

◆ SCB_CFSR_NOCP_Msk [5/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 792 of file core_cm35p.h.

◆ SCB_CFSR_NOCP_Msk [6/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 669 of file core_cm4.h.

◆ SCB_CFSR_NOCP_Msk [7/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 722 of file core_cm7.h.

◆ SCB_CFSR_NOCP_Msk [8/8]

#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

Definition at line 602 of file core_sc300.h.

◆ SCB_CFSR_NOCP_Pos [1/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 800 of file core_armv81mml.h.

◆ SCB_CFSR_NOCP_Pos [2/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 791 of file core_armv8mml.h.

◆ SCB_CFSR_NOCP_Pos [3/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 604 of file core_cm3.h.

◆ SCB_CFSR_NOCP_Pos [4/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 791 of file core_cm33.h.

◆ SCB_CFSR_NOCP_Pos [5/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 791 of file core_cm35p.h.

◆ SCB_CFSR_NOCP_Pos [6/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 668 of file core_cm4.h.

◆ SCB_CFSR_NOCP_Pos [7/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 721 of file core_cm7.h.

◆ SCB_CFSR_NOCP_Pos [8/8]

#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

Definition at line 601 of file core_sc300.h.

◆ SCB_CFSR_PRECISERR_Msk [1/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 785 of file core_armv81mml.h.

◆ SCB_CFSR_PRECISERR_Msk [2/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 776 of file core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Msk [3/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 592 of file core_cm3.h.

◆ SCB_CFSR_PRECISERR_Msk [4/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 776 of file core_cm33.h.

◆ SCB_CFSR_PRECISERR_Msk [5/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 776 of file core_cm35p.h.

◆ SCB_CFSR_PRECISERR_Msk [6/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 656 of file core_cm4.h.

◆ SCB_CFSR_PRECISERR_Msk [7/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 709 of file core_cm7.h.

◆ SCB_CFSR_PRECISERR_Msk [8/8]

#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

Definition at line 589 of file core_sc300.h.

◆ SCB_CFSR_PRECISERR_Pos [1/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 784 of file core_armv81mml.h.

◆ SCB_CFSR_PRECISERR_Pos [2/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 775 of file core_armv8mml.h.

◆ SCB_CFSR_PRECISERR_Pos [3/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 591 of file core_cm3.h.

◆ SCB_CFSR_PRECISERR_Pos [4/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 775 of file core_cm33.h.

◆ SCB_CFSR_PRECISERR_Pos [5/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 775 of file core_cm35p.h.

◆ SCB_CFSR_PRECISERR_Pos [6/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 655 of file core_cm4.h.

◆ SCB_CFSR_PRECISERR_Pos [7/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 708 of file core_cm7.h.

◆ SCB_CFSR_PRECISERR_Pos [8/8]

#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

Definition at line 588 of file core_sc300.h.

◆ SCB_CFSR_STKERR_Msk [1/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 776 of file core_armv81mml.h.

◆ SCB_CFSR_STKERR_Msk [2/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 767 of file core_armv8mml.h.

◆ SCB_CFSR_STKERR_Msk [3/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 583 of file core_cm3.h.

◆ SCB_CFSR_STKERR_Msk [4/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 767 of file core_cm33.h.

◆ SCB_CFSR_STKERR_Msk [5/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 767 of file core_cm35p.h.

◆ SCB_CFSR_STKERR_Msk [6/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 647 of file core_cm4.h.

◆ SCB_CFSR_STKERR_Msk [7/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 700 of file core_cm7.h.

◆ SCB_CFSR_STKERR_Msk [8/8]

#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

Definition at line 580 of file core_sc300.h.

◆ SCB_CFSR_STKERR_Pos [1/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 775 of file core_armv81mml.h.

◆ SCB_CFSR_STKERR_Pos [2/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 766 of file core_armv8mml.h.

◆ SCB_CFSR_STKERR_Pos [3/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 582 of file core_cm3.h.

◆ SCB_CFSR_STKERR_Pos [4/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 766 of file core_cm33.h.

◆ SCB_CFSR_STKERR_Pos [5/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 766 of file core_cm35p.h.

◆ SCB_CFSR_STKERR_Pos [6/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 646 of file core_cm4.h.

◆ SCB_CFSR_STKERR_Pos [7/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 699 of file core_cm7.h.

◆ SCB_CFSR_STKERR_Pos [8/8]

#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

Definition at line 579 of file core_sc300.h.

◆ SCB_CFSR_STKOF_Msk [1/4]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 798 of file core_armv81mml.h.

◆ SCB_CFSR_STKOF_Msk [2/4]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 789 of file core_armv8mml.h.

◆ SCB_CFSR_STKOF_Msk [3/4]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 789 of file core_cm33.h.

◆ SCB_CFSR_STKOF_Msk [4/4]

#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)

SCB CFSR (UFSR): STKOF Mask

Definition at line 789 of file core_cm35p.h.

◆ SCB_CFSR_STKOF_Pos [1/4]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 797 of file core_armv81mml.h.

◆ SCB_CFSR_STKOF_Pos [2/4]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 788 of file core_armv8mml.h.

◆ SCB_CFSR_STKOF_Pos [3/4]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 788 of file core_cm33.h.

◆ SCB_CFSR_STKOF_Pos [4/4]

#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)

SCB CFSR (UFSR): STKOF Position

Definition at line 788 of file core_cm35p.h.

◆ SCB_CFSR_UNALIGNED_Msk [1/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 795 of file core_armv81mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [2/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 786 of file core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Msk [3/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 602 of file core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Msk [4/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 786 of file core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Msk [5/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 786 of file core_cm35p.h.

◆ SCB_CFSR_UNALIGNED_Msk [6/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 666 of file core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Msk [7/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 719 of file core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Msk [8/8]

#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

Definition at line 599 of file core_sc300.h.

◆ SCB_CFSR_UNALIGNED_Pos [1/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 794 of file core_armv81mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [2/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 785 of file core_armv8mml.h.

◆ SCB_CFSR_UNALIGNED_Pos [3/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 601 of file core_cm3.h.

◆ SCB_CFSR_UNALIGNED_Pos [4/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 785 of file core_cm33.h.

◆ SCB_CFSR_UNALIGNED_Pos [5/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 785 of file core_cm35p.h.

◆ SCB_CFSR_UNALIGNED_Pos [6/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 665 of file core_cm4.h.

◆ SCB_CFSR_UNALIGNED_Pos [7/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 718 of file core_cm7.h.

◆ SCB_CFSR_UNALIGNED_Pos [8/8]

#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

Definition at line 598 of file core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [1/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 810 of file core_armv81mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [2/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 801 of file core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [3/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 614 of file core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [4/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 801 of file core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [5/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 801 of file core_cm35p.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [6/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 678 of file core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [7/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 731 of file core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Msk [8/8]

#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

Definition at line 611 of file core_sc300.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [1/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 809 of file core_armv81mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [2/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 800 of file core_armv8mml.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [3/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 613 of file core_cm3.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [4/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 800 of file core_cm33.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [5/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 800 of file core_cm35p.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [6/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 677 of file core_cm4.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [7/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 730 of file core_cm7.h.

◆ SCB_CFSR_UNDEFINSTR_Pos [8/8]

#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

Definition at line 610 of file core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Msk [1/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 779 of file core_armv81mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [2/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 770 of file core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Msk [3/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 586 of file core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Msk [4/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 770 of file core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Msk [5/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 770 of file core_cm35p.h.

◆ SCB_CFSR_UNSTKERR_Msk [6/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 650 of file core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Msk [7/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 703 of file core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Msk [8/8]

#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

Definition at line 583 of file core_sc300.h.

◆ SCB_CFSR_UNSTKERR_Pos [1/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 778 of file core_armv81mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [2/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 769 of file core_armv8mml.h.

◆ SCB_CFSR_UNSTKERR_Pos [3/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 585 of file core_cm3.h.

◆ SCB_CFSR_UNSTKERR_Pos [4/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 769 of file core_cm33.h.

◆ SCB_CFSR_UNSTKERR_Pos [5/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 769 of file core_cm35p.h.

◆ SCB_CFSR_UNSTKERR_Pos [6/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 649 of file core_cm4.h.

◆ SCB_CFSR_UNSTKERR_Pos [7/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 702 of file core_cm7.h.

◆ SCB_CFSR_UNSTKERR_Pos [8/8]

#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

Definition at line 582 of file core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Msk [1/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 741 of file core_armv81mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [2/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 732 of file core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Msk [3/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 554 of file core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Msk [4/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 732 of file core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Msk [5/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 732 of file core_cm35p.h.

◆ SCB_CFSR_USGFAULTSR_Msk [6/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 612 of file core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Msk [7/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 665 of file core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Msk [8/8]

#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)

SCB CFSR: Usage Fault Status Register Mask

Definition at line 551 of file core_sc300.h.

◆ SCB_CFSR_USGFAULTSR_Pos [1/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 740 of file core_armv81mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [2/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 731 of file core_armv8mml.h.

◆ SCB_CFSR_USGFAULTSR_Pos [3/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 553 of file core_cm3.h.

◆ SCB_CFSR_USGFAULTSR_Pos [4/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 731 of file core_cm33.h.

◆ SCB_CFSR_USGFAULTSR_Pos [5/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 731 of file core_cm35p.h.

◆ SCB_CFSR_USGFAULTSR_Pos [6/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 611 of file core_cm4.h.

◆ SCB_CFSR_USGFAULTSR_Pos [7/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 664 of file core_cm7.h.

◆ SCB_CFSR_USGFAULTSR_Pos [8/8]

#define SCB_CFSR_USGFAULTSR_Pos 16U

SCB CFSR: Usage Fault Status Register Position

Definition at line 550 of file core_sc300.h.

◆ SCB_CLIDR_LOC_Msk [1/5]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 853 of file core_armv81mml.h.

◆ SCB_CLIDR_LOC_Msk [2/5]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 844 of file core_armv8mml.h.

◆ SCB_CLIDR_LOC_Msk [3/5]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 844 of file core_cm33.h.

◆ SCB_CLIDR_LOC_Msk [4/5]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 844 of file core_cm35p.h.

◆ SCB_CLIDR_LOC_Msk [5/5]

#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)

SCB CLIDR: LoC Mask

Definition at line 764 of file core_cm7.h.

◆ SCB_CLIDR_LOC_Pos [1/5]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 852 of file core_armv81mml.h.

◆ SCB_CLIDR_LOC_Pos [2/5]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 843 of file core_armv8mml.h.

◆ SCB_CLIDR_LOC_Pos [3/5]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 843 of file core_cm33.h.

◆ SCB_CLIDR_LOC_Pos [4/5]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 843 of file core_cm35p.h.

◆ SCB_CLIDR_LOC_Pos [5/5]

#define SCB_CLIDR_LOC_Pos 24U

SCB CLIDR: LoC Position

Definition at line 763 of file core_cm7.h.

◆ SCB_CLIDR_LOUU_Msk [1/5]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 850 of file core_armv81mml.h.

◆ SCB_CLIDR_LOUU_Msk [2/5]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 841 of file core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Msk [3/5]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 841 of file core_cm33.h.

◆ SCB_CLIDR_LOUU_Msk [4/5]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 841 of file core_cm35p.h.

◆ SCB_CLIDR_LOUU_Msk [5/5]

#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)

SCB CLIDR: LoUU Mask

Definition at line 761 of file core_cm7.h.

◆ SCB_CLIDR_LOUU_Pos [1/5]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 849 of file core_armv81mml.h.

◆ SCB_CLIDR_LOUU_Pos [2/5]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 840 of file core_armv8mml.h.

◆ SCB_CLIDR_LOUU_Pos [3/5]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 840 of file core_cm33.h.

◆ SCB_CLIDR_LOUU_Pos [4/5]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 840 of file core_cm35p.h.

◆ SCB_CLIDR_LOUU_Pos [5/5]

#define SCB_CLIDR_LOUU_Pos 27U

SCB CLIDR: LoUU Position

Definition at line 760 of file core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [1/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 560 of file core_armv81mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [2/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [3/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 551 of file core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [4/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [5/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 380 of file core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [6/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 362 of file core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [7/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 406 of file core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [8/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 407 of file core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [9/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 551 of file core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [10/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 551 of file core_cm35p.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [11/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 473 of file core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [12/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 517 of file core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [13/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 370 of file core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Msk [14/14]

#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)

SCB CPUID: ARCHITECTURE Mask

Definition at line 409 of file core_sc300.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [1/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 559 of file core_armv81mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [2/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file core_armv8mbl.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [3/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 550 of file core_armv8mml.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [4/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file core_cm0.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [5/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 379 of file core_cm0plus.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [6/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 361 of file core_cm1.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [7/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 405 of file core_cm23.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [8/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 406 of file core_cm3.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [9/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 550 of file core_cm33.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [10/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 550 of file core_cm35p.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [11/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 472 of file core_cm4.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [12/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 516 of file core_cm7.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [13/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 369 of file core_sc000.h.

◆ SCB_CPUID_ARCHITECTURE_Pos [14/14]

#define SCB_CPUID_ARCHITECTURE_Pos 16U

SCB CPUID: ARCHITECTURE Position

Definition at line 408 of file core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [1/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 554 of file core_armv81mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [2/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [3/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 545 of file core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [4/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [5/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 374 of file core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [6/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 356 of file core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [7/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 400 of file core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [8/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 401 of file core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [9/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 545 of file core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [10/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 545 of file core_cm35p.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [11/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 467 of file core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [12/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 511 of file core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [13/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 364 of file core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Msk [14/14]

#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)

SCB CPUID: IMPLEMENTER Mask

Definition at line 403 of file core_sc300.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [1/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 553 of file core_armv81mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [2/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file core_armv8mbl.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [3/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 544 of file core_armv8mml.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [4/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file core_cm0.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [5/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 373 of file core_cm0plus.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [6/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 355 of file core_cm1.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [7/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 399 of file core_cm23.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [8/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 400 of file core_cm3.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [9/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 544 of file core_cm33.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [10/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 544 of file core_cm35p.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [11/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 466 of file core_cm4.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [12/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 510 of file core_cm7.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [13/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 363 of file core_sc000.h.

◆ SCB_CPUID_IMPLEMENTER_Pos [14/14]

#define SCB_CPUID_IMPLEMENTER_Pos 24U

SCB CPUID: IMPLEMENTER Position

Definition at line 402 of file core_sc300.h.

◆ SCB_CPUID_PARTNO_Msk [1/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 563 of file core_armv81mml.h.

◆ SCB_CPUID_PARTNO_Msk [2/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Msk [3/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 554 of file core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Msk [4/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file core_cm0.h.

◆ SCB_CPUID_PARTNO_Msk [5/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 383 of file core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Msk [6/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 365 of file core_cm1.h.

◆ SCB_CPUID_PARTNO_Msk [7/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 409 of file core_cm23.h.

◆ SCB_CPUID_PARTNO_Msk [8/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 410 of file core_cm3.h.

◆ SCB_CPUID_PARTNO_Msk [9/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 554 of file core_cm33.h.

◆ SCB_CPUID_PARTNO_Msk [10/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 554 of file core_cm35p.h.

◆ SCB_CPUID_PARTNO_Msk [11/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 476 of file core_cm4.h.

◆ SCB_CPUID_PARTNO_Msk [12/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 520 of file core_cm7.h.

◆ SCB_CPUID_PARTNO_Msk [13/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 373 of file core_sc000.h.

◆ SCB_CPUID_PARTNO_Msk [14/14]

#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)

SCB CPUID: PARTNO Mask

Definition at line 412 of file core_sc300.h.

◆ SCB_CPUID_PARTNO_Pos [1/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 562 of file core_armv81mml.h.

◆ SCB_CPUID_PARTNO_Pos [2/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 408 of file core_armv8mbl.h.

◆ SCB_CPUID_PARTNO_Pos [3/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 553 of file core_armv8mml.h.

◆ SCB_CPUID_PARTNO_Pos [4/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 364 of file core_cm0.h.

◆ SCB_CPUID_PARTNO_Pos [5/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 382 of file core_cm0plus.h.

◆ SCB_CPUID_PARTNO_Pos [6/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 364 of file core_cm1.h.

◆ SCB_CPUID_PARTNO_Pos [7/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 408 of file core_cm23.h.

◆ SCB_CPUID_PARTNO_Pos [8/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 409 of file core_cm3.h.

◆ SCB_CPUID_PARTNO_Pos [9/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 553 of file core_cm33.h.

◆ SCB_CPUID_PARTNO_Pos [10/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 553 of file core_cm35p.h.

◆ SCB_CPUID_PARTNO_Pos [11/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 475 of file core_cm4.h.

◆ SCB_CPUID_PARTNO_Pos [12/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 519 of file core_cm7.h.

◆ SCB_CPUID_PARTNO_Pos [13/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 372 of file core_sc000.h.

◆ SCB_CPUID_PARTNO_Pos [14/14]

#define SCB_CPUID_PARTNO_Pos 4U

SCB CPUID: PARTNO Position

Definition at line 411 of file core_sc300.h.

◆ SCB_CPUID_REVISION_Msk [1/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 566 of file core_armv81mml.h.

◆ SCB_CPUID_REVISION_Msk [2/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Msk [3/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 557 of file core_armv8mml.h.

◆ SCB_CPUID_REVISION_Msk [4/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file core_cm0.h.

◆ SCB_CPUID_REVISION_Msk [5/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 386 of file core_cm0plus.h.

◆ SCB_CPUID_REVISION_Msk [6/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 368 of file core_cm1.h.

◆ SCB_CPUID_REVISION_Msk [7/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 412 of file core_cm23.h.

◆ SCB_CPUID_REVISION_Msk [8/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 413 of file core_cm3.h.

◆ SCB_CPUID_REVISION_Msk [9/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 557 of file core_cm33.h.

◆ SCB_CPUID_REVISION_Msk [10/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 557 of file core_cm35p.h.

◆ SCB_CPUID_REVISION_Msk [11/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 479 of file core_cm4.h.

◆ SCB_CPUID_REVISION_Msk [12/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 523 of file core_cm7.h.

◆ SCB_CPUID_REVISION_Msk [13/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 376 of file core_sc000.h.

◆ SCB_CPUID_REVISION_Msk [14/14]

#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)

SCB CPUID: REVISION Mask

Definition at line 415 of file core_sc300.h.

◆ SCB_CPUID_REVISION_Pos [1/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 565 of file core_armv81mml.h.

◆ SCB_CPUID_REVISION_Pos [2/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 411 of file core_armv8mbl.h.

◆ SCB_CPUID_REVISION_Pos [3/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 556 of file core_armv8mml.h.

◆ SCB_CPUID_REVISION_Pos [4/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 367 of file core_cm0.h.

◆ SCB_CPUID_REVISION_Pos [5/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 385 of file core_cm0plus.h.

◆ SCB_CPUID_REVISION_Pos [6/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 367 of file core_cm1.h.

◆ SCB_CPUID_REVISION_Pos [7/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 411 of file core_cm23.h.

◆ SCB_CPUID_REVISION_Pos [8/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 412 of file core_cm3.h.

◆ SCB_CPUID_REVISION_Pos [9/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 556 of file core_cm33.h.

◆ SCB_CPUID_REVISION_Pos [10/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 556 of file core_cm35p.h.

◆ SCB_CPUID_REVISION_Pos [11/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 478 of file core_cm4.h.

◆ SCB_CPUID_REVISION_Pos [12/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 522 of file core_cm7.h.

◆ SCB_CPUID_REVISION_Pos [13/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 375 of file core_sc000.h.

◆ SCB_CPUID_REVISION_Pos [14/14]

#define SCB_CPUID_REVISION_Pos 0U

SCB CPUID: REVISION Position

Definition at line 414 of file core_sc300.h.

◆ SCB_CPUID_VARIANT_Msk [1/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 557 of file core_armv81mml.h.

◆ SCB_CPUID_VARIANT_Msk [2/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Msk [3/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 548 of file core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Msk [4/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file core_cm0.h.

◆ SCB_CPUID_VARIANT_Msk [5/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 377 of file core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Msk [6/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 359 of file core_cm1.h.

◆ SCB_CPUID_VARIANT_Msk [7/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 403 of file core_cm23.h.

◆ SCB_CPUID_VARIANT_Msk [8/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 404 of file core_cm3.h.

◆ SCB_CPUID_VARIANT_Msk [9/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 548 of file core_cm33.h.

◆ SCB_CPUID_VARIANT_Msk [10/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 548 of file core_cm35p.h.

◆ SCB_CPUID_VARIANT_Msk [11/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 470 of file core_cm4.h.

◆ SCB_CPUID_VARIANT_Msk [12/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 514 of file core_cm7.h.

◆ SCB_CPUID_VARIANT_Msk [13/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 367 of file core_sc000.h.

◆ SCB_CPUID_VARIANT_Msk [14/14]

#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)

SCB CPUID: VARIANT Mask

Definition at line 406 of file core_sc300.h.

◆ SCB_CPUID_VARIANT_Pos [1/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 556 of file core_armv81mml.h.

◆ SCB_CPUID_VARIANT_Pos [2/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 402 of file core_armv8mbl.h.

◆ SCB_CPUID_VARIANT_Pos [3/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 547 of file core_armv8mml.h.

◆ SCB_CPUID_VARIANT_Pos [4/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 358 of file core_cm0.h.

◆ SCB_CPUID_VARIANT_Pos [5/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 376 of file core_cm0plus.h.

◆ SCB_CPUID_VARIANT_Pos [6/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 358 of file core_cm1.h.

◆ SCB_CPUID_VARIANT_Pos [7/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 402 of file core_cm23.h.

◆ SCB_CPUID_VARIANT_Pos [8/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 403 of file core_cm3.h.

◆ SCB_CPUID_VARIANT_Pos [9/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 547 of file core_cm33.h.

◆ SCB_CPUID_VARIANT_Pos [10/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 547 of file core_cm35p.h.

◆ SCB_CPUID_VARIANT_Pos [11/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 469 of file core_cm4.h.

◆ SCB_CPUID_VARIANT_Pos [12/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 513 of file core_cm7.h.

◆ SCB_CPUID_VARIANT_Pos [13/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 366 of file core_sc000.h.

◆ SCB_CPUID_VARIANT_Pos [14/14]

#define SCB_CPUID_VARIANT_Pos 20U

SCB CPUID: VARIANT Position

Definition at line 405 of file core_sc300.h.

◆ SCB_CSSELR_IND_Msk [1/5]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 898 of file core_armv81mml.h.

◆ SCB_CSSELR_IND_Msk [2/5]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 889 of file core_armv8mml.h.

◆ SCB_CSSELR_IND_Msk [3/5]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 889 of file core_cm33.h.

◆ SCB_CSSELR_IND_Msk [4/5]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 889 of file core_cm35p.h.

◆ SCB_CSSELR_IND_Msk [5/5]

#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)

SCB CSSELR: InD Mask

Definition at line 809 of file core_cm7.h.

◆ SCB_CSSELR_IND_Pos [1/5]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 897 of file core_armv81mml.h.

◆ SCB_CSSELR_IND_Pos [2/5]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 888 of file core_armv8mml.h.

◆ SCB_CSSELR_IND_Pos [3/5]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 888 of file core_cm33.h.

◆ SCB_CSSELR_IND_Pos [4/5]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 888 of file core_cm35p.h.

◆ SCB_CSSELR_IND_Pos [5/5]

#define SCB_CSSELR_IND_Pos 0U

SCB CSSELR: InD Position

Definition at line 808 of file core_cm7.h.

◆ SCB_CSSELR_LEVEL_Msk [1/5]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 895 of file core_armv81mml.h.

◆ SCB_CSSELR_LEVEL_Msk [2/5]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 886 of file core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Msk [3/5]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 886 of file core_cm33.h.

◆ SCB_CSSELR_LEVEL_Msk [4/5]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 886 of file core_cm35p.h.

◆ SCB_CSSELR_LEVEL_Msk [5/5]

#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)

SCB CSSELR: Level Mask

Definition at line 806 of file core_cm7.h.

◆ SCB_CSSELR_LEVEL_Pos [1/5]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 894 of file core_armv81mml.h.

◆ SCB_CSSELR_LEVEL_Pos [2/5]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 885 of file core_armv8mml.h.

◆ SCB_CSSELR_LEVEL_Pos [3/5]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 885 of file core_cm33.h.

◆ SCB_CSSELR_LEVEL_Pos [4/5]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 885 of file core_cm35p.h.

◆ SCB_CSSELR_LEVEL_Pos [5/5]

#define SCB_CSSELR_LEVEL_Pos 1U

SCB CSSELR: Level Position

Definition at line 805 of file core_cm7.h.

◆ SCB_CTR_CWG_Msk [1/5]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 860 of file core_armv81mml.h.

◆ SCB_CTR_CWG_Msk [2/5]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 851 of file core_armv8mml.h.

◆ SCB_CTR_CWG_Msk [3/5]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 851 of file core_cm33.h.

◆ SCB_CTR_CWG_Msk [4/5]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 851 of file core_cm35p.h.

◆ SCB_CTR_CWG_Msk [5/5]

#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)

SCB CTR: CWG Mask

Definition at line 771 of file core_cm7.h.

◆ SCB_CTR_CWG_Pos [1/5]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 859 of file core_armv81mml.h.

◆ SCB_CTR_CWG_Pos [2/5]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 850 of file core_armv8mml.h.

◆ SCB_CTR_CWG_Pos [3/5]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 850 of file core_cm33.h.

◆ SCB_CTR_CWG_Pos [4/5]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 850 of file core_cm35p.h.

◆ SCB_CTR_CWG_Pos [5/5]

#define SCB_CTR_CWG_Pos 24U

SCB CTR: CWG Position

Definition at line 770 of file core_cm7.h.

◆ SCB_CTR_DMINLINE_Msk [1/5]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 866 of file core_armv81mml.h.

◆ SCB_CTR_DMINLINE_Msk [2/5]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 857 of file core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Msk [3/5]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 857 of file core_cm33.h.

◆ SCB_CTR_DMINLINE_Msk [4/5]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 857 of file core_cm35p.h.

◆ SCB_CTR_DMINLINE_Msk [5/5]

#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)

SCB CTR: DminLine Mask

Definition at line 777 of file core_cm7.h.

◆ SCB_CTR_DMINLINE_Pos [1/5]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 865 of file core_armv81mml.h.

◆ SCB_CTR_DMINLINE_Pos [2/5]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 856 of file core_armv8mml.h.

◆ SCB_CTR_DMINLINE_Pos [3/5]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 856 of file core_cm33.h.

◆ SCB_CTR_DMINLINE_Pos [4/5]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 856 of file core_cm35p.h.

◆ SCB_CTR_DMINLINE_Pos [5/5]

#define SCB_CTR_DMINLINE_Pos 16U

SCB CTR: DminLine Position

Definition at line 776 of file core_cm7.h.

◆ SCB_CTR_ERG_Msk [1/5]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 863 of file core_armv81mml.h.

◆ SCB_CTR_ERG_Msk [2/5]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 854 of file core_armv8mml.h.

◆ SCB_CTR_ERG_Msk [3/5]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 854 of file core_cm33.h.

◆ SCB_CTR_ERG_Msk [4/5]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 854 of file core_cm35p.h.

◆ SCB_CTR_ERG_Msk [5/5]

#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)

SCB CTR: ERG Mask

Definition at line 774 of file core_cm7.h.

◆ SCB_CTR_ERG_Pos [1/5]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 862 of file core_armv81mml.h.

◆ SCB_CTR_ERG_Pos [2/5]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 853 of file core_armv8mml.h.

◆ SCB_CTR_ERG_Pos [3/5]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 853 of file core_cm33.h.

◆ SCB_CTR_ERG_Pos [4/5]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 853 of file core_cm35p.h.

◆ SCB_CTR_ERG_Pos [5/5]

#define SCB_CTR_ERG_Pos 20U

SCB CTR: ERG Position

Definition at line 773 of file core_cm7.h.

◆ SCB_CTR_FORMAT_Msk [1/5]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 857 of file core_armv81mml.h.

◆ SCB_CTR_FORMAT_Msk [2/5]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 848 of file core_armv8mml.h.

◆ SCB_CTR_FORMAT_Msk [3/5]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 848 of file core_cm33.h.

◆ SCB_CTR_FORMAT_Msk [4/5]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 848 of file core_cm35p.h.

◆ SCB_CTR_FORMAT_Msk [5/5]

#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)

SCB CTR: Format Mask

Definition at line 768 of file core_cm7.h.

◆ SCB_CTR_FORMAT_Pos [1/5]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 856 of file core_armv81mml.h.

◆ SCB_CTR_FORMAT_Pos [2/5]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 847 of file core_armv8mml.h.

◆ SCB_CTR_FORMAT_Pos [3/5]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 847 of file core_cm33.h.

◆ SCB_CTR_FORMAT_Pos [4/5]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 847 of file core_cm35p.h.

◆ SCB_CTR_FORMAT_Pos [5/5]

#define SCB_CTR_FORMAT_Pos 29U

SCB CTR: Format Position

Definition at line 767 of file core_cm7.h.

◆ SCB_CTR_IMINLINE_Msk [1/5]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 869 of file core_armv81mml.h.

◆ SCB_CTR_IMINLINE_Msk [2/5]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 860 of file core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Msk [3/5]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 860 of file core_cm33.h.

◆ SCB_CTR_IMINLINE_Msk [4/5]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 860 of file core_cm35p.h.

◆ SCB_CTR_IMINLINE_Msk [5/5]

#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)

SCB CTR: ImInLine Mask

Definition at line 780 of file core_cm7.h.

◆ SCB_CTR_IMINLINE_Pos [1/5]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 868 of file core_armv81mml.h.

◆ SCB_CTR_IMINLINE_Pos [2/5]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 859 of file core_armv8mml.h.

◆ SCB_CTR_IMINLINE_Pos [3/5]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 859 of file core_cm33.h.

◆ SCB_CTR_IMINLINE_Pos [4/5]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 859 of file core_cm35p.h.

◆ SCB_CTR_IMINLINE_Pos [5/5]

#define SCB_CTR_IMINLINE_Pos 0U

SCB CTR: ImInLine Position

Definition at line 779 of file core_cm7.h.

◆ SCB_DCCISW_SET_Msk [1/5]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 923 of file core_armv81mml.h.

◆ SCB_DCCISW_SET_Msk [2/5]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 914 of file core_armv8mml.h.

◆ SCB_DCCISW_SET_Msk [3/5]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 914 of file core_cm33.h.

◆ SCB_DCCISW_SET_Msk [4/5]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 914 of file core_cm35p.h.

◆ SCB_DCCISW_SET_Msk [5/5]

#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)

SCB DCCISW: Set Mask

Definition at line 834 of file core_cm7.h.

◆ SCB_DCCISW_SET_Pos [1/5]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 922 of file core_armv81mml.h.

◆ SCB_DCCISW_SET_Pos [2/5]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 913 of file core_armv8mml.h.

◆ SCB_DCCISW_SET_Pos [3/5]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 913 of file core_cm33.h.

◆ SCB_DCCISW_SET_Pos [4/5]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 913 of file core_cm35p.h.

◆ SCB_DCCISW_SET_Pos [5/5]

#define SCB_DCCISW_SET_Pos 5U

SCB DCCISW: Set Position

Definition at line 833 of file core_cm7.h.

◆ SCB_DCCISW_WAY_Msk [1/5]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 920 of file core_armv81mml.h.

◆ SCB_DCCISW_WAY_Msk [2/5]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 911 of file core_armv8mml.h.

◆ SCB_DCCISW_WAY_Msk [3/5]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 911 of file core_cm33.h.

◆ SCB_DCCISW_WAY_Msk [4/5]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 911 of file core_cm35p.h.

◆ SCB_DCCISW_WAY_Msk [5/5]

#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)

SCB DCCISW: Way Mask

Definition at line 831 of file core_cm7.h.

◆ SCB_DCCISW_WAY_Pos [1/5]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 919 of file core_armv81mml.h.

◆ SCB_DCCISW_WAY_Pos [2/5]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 910 of file core_armv8mml.h.

◆ SCB_DCCISW_WAY_Pos [3/5]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 910 of file core_cm33.h.

◆ SCB_DCCISW_WAY_Pos [4/5]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 910 of file core_cm35p.h.

◆ SCB_DCCISW_WAY_Pos [5/5]

#define SCB_DCCISW_WAY_Pos 30U

SCB DCCISW: Way Position

Definition at line 830 of file core_cm7.h.

◆ SCB_DCCSW_SET_Msk [1/5]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 916 of file core_armv81mml.h.

◆ SCB_DCCSW_SET_Msk [2/5]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 907 of file core_armv8mml.h.

◆ SCB_DCCSW_SET_Msk [3/5]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 907 of file core_cm33.h.

◆ SCB_DCCSW_SET_Msk [4/5]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 907 of file core_cm35p.h.

◆ SCB_DCCSW_SET_Msk [5/5]

#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)

SCB DCCSW: Set Mask

Definition at line 827 of file core_cm7.h.

◆ SCB_DCCSW_SET_Pos [1/5]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 915 of file core_armv81mml.h.

◆ SCB_DCCSW_SET_Pos [2/5]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 906 of file core_armv8mml.h.

◆ SCB_DCCSW_SET_Pos [3/5]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 906 of file core_cm33.h.

◆ SCB_DCCSW_SET_Pos [4/5]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 906 of file core_cm35p.h.

◆ SCB_DCCSW_SET_Pos [5/5]

#define SCB_DCCSW_SET_Pos 5U

SCB DCCSW: Set Position

Definition at line 826 of file core_cm7.h.

◆ SCB_DCCSW_WAY_Msk [1/5]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 913 of file core_armv81mml.h.

◆ SCB_DCCSW_WAY_Msk [2/5]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 904 of file core_armv8mml.h.

◆ SCB_DCCSW_WAY_Msk [3/5]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 904 of file core_cm33.h.

◆ SCB_DCCSW_WAY_Msk [4/5]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 904 of file core_cm35p.h.

◆ SCB_DCCSW_WAY_Msk [5/5]

#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)

SCB DCCSW: Way Mask

Definition at line 824 of file core_cm7.h.

◆ SCB_DCCSW_WAY_Pos [1/5]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 912 of file core_armv81mml.h.

◆ SCB_DCCSW_WAY_Pos [2/5]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 903 of file core_armv8mml.h.

◆ SCB_DCCSW_WAY_Pos [3/5]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 903 of file core_cm33.h.

◆ SCB_DCCSW_WAY_Pos [4/5]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 903 of file core_cm35p.h.

◆ SCB_DCCSW_WAY_Pos [5/5]

#define SCB_DCCSW_WAY_Pos 30U

SCB DCCSW: Way Position

Definition at line 823 of file core_cm7.h.

◆ SCB_DCISW_SET_Msk [1/5]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 909 of file core_armv81mml.h.

◆ SCB_DCISW_SET_Msk [2/5]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 900 of file core_armv8mml.h.

◆ SCB_DCISW_SET_Msk [3/5]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 900 of file core_cm33.h.

◆ SCB_DCISW_SET_Msk [4/5]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 900 of file core_cm35p.h.

◆ SCB_DCISW_SET_Msk [5/5]

#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)

SCB DCISW: Set Mask

Definition at line 820 of file core_cm7.h.

◆ SCB_DCISW_SET_Pos [1/5]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 908 of file core_armv81mml.h.

◆ SCB_DCISW_SET_Pos [2/5]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 899 of file core_armv8mml.h.

◆ SCB_DCISW_SET_Pos [3/5]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 899 of file core_cm33.h.

◆ SCB_DCISW_SET_Pos [4/5]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 899 of file core_cm35p.h.

◆ SCB_DCISW_SET_Pos [5/5]

#define SCB_DCISW_SET_Pos 5U

SCB DCISW: Set Position

Definition at line 819 of file core_cm7.h.

◆ SCB_DCISW_WAY_Msk [1/5]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 906 of file core_armv81mml.h.

◆ SCB_DCISW_WAY_Msk [2/5]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 897 of file core_armv8mml.h.

◆ SCB_DCISW_WAY_Msk [3/5]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 897 of file core_cm33.h.

◆ SCB_DCISW_WAY_Msk [4/5]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 897 of file core_cm35p.h.

◆ SCB_DCISW_WAY_Msk [5/5]

#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)

SCB DCISW: Way Mask

Definition at line 817 of file core_cm7.h.

◆ SCB_DCISW_WAY_Pos [1/5]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 905 of file core_armv81mml.h.

◆ SCB_DCISW_WAY_Pos [2/5]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 896 of file core_armv8mml.h.

◆ SCB_DCISW_WAY_Pos [3/5]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 896 of file core_cm33.h.

◆ SCB_DCISW_WAY_Pos [4/5]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 896 of file core_cm35p.h.

◆ SCB_DCISW_WAY_Pos [5/5]

#define SCB_DCISW_WAY_Pos 30U

SCB DCISW: Way Position

Definition at line 816 of file core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [1/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 833 of file core_armv81mml.h.

◆ SCB_DFSR_BKPT_Msk [2/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 824 of file core_armv8mml.h.

◆ SCB_DFSR_BKPT_Msk [3/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 637 of file core_cm3.h.

◆ SCB_DFSR_BKPT_Msk [4/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 824 of file core_cm33.h.

◆ SCB_DFSR_BKPT_Msk [5/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 824 of file core_cm35p.h.

◆ SCB_DFSR_BKPT_Msk [6/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 701 of file core_cm4.h.

◆ SCB_DFSR_BKPT_Msk [7/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 754 of file core_cm7.h.

◆ SCB_DFSR_BKPT_Msk [8/8]

#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)

SCB DFSR: BKPT Mask

Definition at line 634 of file core_sc300.h.

◆ SCB_DFSR_BKPT_Pos [1/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 832 of file core_armv81mml.h.

◆ SCB_DFSR_BKPT_Pos [2/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 823 of file core_armv8mml.h.

◆ SCB_DFSR_BKPT_Pos [3/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 636 of file core_cm3.h.

◆ SCB_DFSR_BKPT_Pos [4/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 823 of file core_cm33.h.

◆ SCB_DFSR_BKPT_Pos [5/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 823 of file core_cm35p.h.

◆ SCB_DFSR_BKPT_Pos [6/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 700 of file core_cm4.h.

◆ SCB_DFSR_BKPT_Pos [7/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 753 of file core_cm7.h.

◆ SCB_DFSR_BKPT_Pos [8/8]

#define SCB_DFSR_BKPT_Pos 1U

SCB DFSR: BKPT Position

Definition at line 633 of file core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Msk [1/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 830 of file core_armv81mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [2/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 821 of file core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Msk [3/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 634 of file core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Msk [4/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 821 of file core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Msk [5/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 821 of file core_cm35p.h.

◆ SCB_DFSR_DWTTRAP_Msk [6/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 698 of file core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Msk [7/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 751 of file core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Msk [8/8]

#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)

SCB DFSR: DWTTRAP Mask

Definition at line 631 of file core_sc300.h.

◆ SCB_DFSR_DWTTRAP_Pos [1/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 829 of file core_armv81mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [2/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 820 of file core_armv8mml.h.

◆ SCB_DFSR_DWTTRAP_Pos [3/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 633 of file core_cm3.h.

◆ SCB_DFSR_DWTTRAP_Pos [4/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 820 of file core_cm33.h.

◆ SCB_DFSR_DWTTRAP_Pos [5/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 820 of file core_cm35p.h.

◆ SCB_DFSR_DWTTRAP_Pos [6/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 697 of file core_cm4.h.

◆ SCB_DFSR_DWTTRAP_Pos [7/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 750 of file core_cm7.h.

◆ SCB_DFSR_DWTTRAP_Pos [8/8]

#define SCB_DFSR_DWTTRAP_Pos 2U

SCB DFSR: DWTTRAP Position

Definition at line 630 of file core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Msk [1/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 824 of file core_armv81mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [2/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 815 of file core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Msk [3/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 628 of file core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Msk [4/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 815 of file core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Msk [5/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 815 of file core_cm35p.h.

◆ SCB_DFSR_EXTERNAL_Msk [6/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 692 of file core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Msk [7/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 745 of file core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Msk [8/8]

#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)

SCB DFSR: EXTERNAL Mask

Definition at line 625 of file core_sc300.h.

◆ SCB_DFSR_EXTERNAL_Pos [1/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 823 of file core_armv81mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [2/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 814 of file core_armv8mml.h.

◆ SCB_DFSR_EXTERNAL_Pos [3/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 627 of file core_cm3.h.

◆ SCB_DFSR_EXTERNAL_Pos [4/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 814 of file core_cm33.h.

◆ SCB_DFSR_EXTERNAL_Pos [5/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 814 of file core_cm35p.h.

◆ SCB_DFSR_EXTERNAL_Pos [6/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 691 of file core_cm4.h.

◆ SCB_DFSR_EXTERNAL_Pos [7/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 744 of file core_cm7.h.

◆ SCB_DFSR_EXTERNAL_Pos [8/8]

#define SCB_DFSR_EXTERNAL_Pos 4U

SCB DFSR: EXTERNAL Position

Definition at line 624 of file core_sc300.h.

◆ SCB_DFSR_HALTED_Msk [1/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 836 of file core_armv81mml.h.

◆ SCB_DFSR_HALTED_Msk [2/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 827 of file core_armv8mml.h.

◆ SCB_DFSR_HALTED_Msk [3/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 640 of file core_cm3.h.

◆ SCB_DFSR_HALTED_Msk [4/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 827 of file core_cm33.h.

◆ SCB_DFSR_HALTED_Msk [5/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 827 of file core_cm35p.h.

◆ SCB_DFSR_HALTED_Msk [6/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 704 of file core_cm4.h.

◆ SCB_DFSR_HALTED_Msk [7/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 757 of file core_cm7.h.

◆ SCB_DFSR_HALTED_Msk [8/8]

#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)

SCB DFSR: HALTED Mask

Definition at line 637 of file core_sc300.h.

◆ SCB_DFSR_HALTED_Pos [1/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 835 of file core_armv81mml.h.

◆ SCB_DFSR_HALTED_Pos [2/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 826 of file core_armv8mml.h.

◆ SCB_DFSR_HALTED_Pos [3/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 639 of file core_cm3.h.

◆ SCB_DFSR_HALTED_Pos [4/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 826 of file core_cm33.h.

◆ SCB_DFSR_HALTED_Pos [5/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 826 of file core_cm35p.h.

◆ SCB_DFSR_HALTED_Pos [6/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 703 of file core_cm4.h.

◆ SCB_DFSR_HALTED_Pos [7/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 756 of file core_cm7.h.

◆ SCB_DFSR_HALTED_Pos [8/8]

#define SCB_DFSR_HALTED_Pos 0U

SCB DFSR: HALTED Position

Definition at line 636 of file core_sc300.h.

◆ SCB_DFSR_VCATCH_Msk [1/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 827 of file core_armv81mml.h.

◆ SCB_DFSR_VCATCH_Msk [2/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 818 of file core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Msk [3/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 631 of file core_cm3.h.

◆ SCB_DFSR_VCATCH_Msk [4/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 818 of file core_cm33.h.

◆ SCB_DFSR_VCATCH_Msk [5/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 818 of file core_cm35p.h.

◆ SCB_DFSR_VCATCH_Msk [6/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 695 of file core_cm4.h.

◆ SCB_DFSR_VCATCH_Msk [7/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 748 of file core_cm7.h.

◆ SCB_DFSR_VCATCH_Msk [8/8]

#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)

SCB DFSR: VCATCH Mask

Definition at line 628 of file core_sc300.h.

◆ SCB_DFSR_VCATCH_Pos [1/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 826 of file core_armv81mml.h.

◆ SCB_DFSR_VCATCH_Pos [2/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 817 of file core_armv8mml.h.

◆ SCB_DFSR_VCATCH_Pos [3/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 630 of file core_cm3.h.

◆ SCB_DFSR_VCATCH_Pos [4/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 817 of file core_cm33.h.

◆ SCB_DFSR_VCATCH_Pos [5/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 817 of file core_cm35p.h.

◆ SCB_DFSR_VCATCH_Pos [6/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 694 of file core_cm4.h.

◆ SCB_DFSR_VCATCH_Pos [7/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 747 of file core_cm7.h.

◆ SCB_DFSR_VCATCH_Pos [8/8]

#define SCB_DFSR_VCATCH_Pos 3U

SCB DFSR: VCATCH Position

Definition at line 627 of file core_sc300.h.

◆ SCB_DTCMCR_EN_Msk [1/2]

#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 949 of file core_armv81mml.h.

◆ SCB_DTCMCR_EN_Msk [2/2]

#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)

SCB DTCMCR: EN Mask

Definition at line 860 of file core_cm7.h.

◆ SCB_DTCMCR_EN_Pos [1/2]

#define SCB_DTCMCR_EN_Pos 0U

SCB DTCMCR: EN Position

Definition at line 948 of file core_armv81mml.h.

◆ SCB_DTCMCR_EN_Pos [2/2]

#define SCB_DTCMCR_EN_Pos 0U

SCB DTCMCR: EN Position

Definition at line 859 of file core_cm7.h.

◆ SCB_DTCMCR_RETEN_Msk [1/2]

#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 943 of file core_armv81mml.h.

◆ SCB_DTCMCR_RETEN_Msk [2/2]

#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)

SCB DTCMCR: RETEN Mask

Definition at line 854 of file core_cm7.h.

◆ SCB_DTCMCR_RETEN_Pos [1/2]

#define SCB_DTCMCR_RETEN_Pos 2U

SCB DTCMCR: RETEN Position

Definition at line 942 of file core_armv81mml.h.

◆ SCB_DTCMCR_RETEN_Pos [2/2]

#define SCB_DTCMCR_RETEN_Pos 2U

SCB DTCMCR: RETEN Position

Definition at line 853 of file core_cm7.h.

◆ SCB_DTCMCR_RMW_Msk [1/2]

#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 946 of file core_armv81mml.h.

◆ SCB_DTCMCR_RMW_Msk [2/2]

#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)

SCB DTCMCR: RMW Mask

Definition at line 857 of file core_cm7.h.

◆ SCB_DTCMCR_RMW_Pos [1/2]

#define SCB_DTCMCR_RMW_Pos 1U

SCB DTCMCR: RMW Position

Definition at line 945 of file core_armv81mml.h.

◆ SCB_DTCMCR_RMW_Pos [2/2]

#define SCB_DTCMCR_RMW_Pos 1U

SCB DTCMCR: RMW Position

Definition at line 856 of file core_cm7.h.

◆ SCB_DTCMCR_SZ_Msk [1/2]

#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 940 of file core_armv81mml.h.

◆ SCB_DTCMCR_SZ_Msk [2/2]

#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)

SCB DTCMCR: SZ Mask

Definition at line 851 of file core_cm7.h.

◆ SCB_DTCMCR_SZ_Pos [1/2]

#define SCB_DTCMCR_SZ_Pos 3U

SCB DTCMCR: SZ Position

Definition at line 939 of file core_armv81mml.h.

◆ SCB_DTCMCR_SZ_Pos [2/2]

#define SCB_DTCMCR_SZ_Pos 3U

SCB DTCMCR: SZ Position

Definition at line 850 of file core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [1/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 814 of file core_armv81mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [2/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 805 of file core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Msk [3/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 618 of file core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Msk [4/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 805 of file core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Msk [5/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 805 of file core_cm35p.h.

◆ SCB_HFSR_DEBUGEVT_Msk [6/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 682 of file core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Msk [7/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 735 of file core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Msk [8/8]

#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)

SCB HFSR: DEBUGEVT Mask

Definition at line 615 of file core_sc300.h.

◆ SCB_HFSR_DEBUGEVT_Pos [1/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 813 of file core_armv81mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [2/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 804 of file core_armv8mml.h.

◆ SCB_HFSR_DEBUGEVT_Pos [3/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 617 of file core_cm3.h.

◆ SCB_HFSR_DEBUGEVT_Pos [4/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 804 of file core_cm33.h.

◆ SCB_HFSR_DEBUGEVT_Pos [5/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 804 of file core_cm35p.h.

◆ SCB_HFSR_DEBUGEVT_Pos [6/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 681 of file core_cm4.h.

◆ SCB_HFSR_DEBUGEVT_Pos [7/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 734 of file core_cm7.h.

◆ SCB_HFSR_DEBUGEVT_Pos [8/8]

#define SCB_HFSR_DEBUGEVT_Pos 31U

SCB HFSR: DEBUGEVT Position

Definition at line 614 of file core_sc300.h.

◆ SCB_HFSR_FORCED_Msk [1/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 817 of file core_armv81mml.h.

◆ SCB_HFSR_FORCED_Msk [2/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 808 of file core_armv8mml.h.

◆ SCB_HFSR_FORCED_Msk [3/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 621 of file core_cm3.h.

◆ SCB_HFSR_FORCED_Msk [4/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 808 of file core_cm33.h.

◆ SCB_HFSR_FORCED_Msk [5/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 808 of file core_cm35p.h.

◆ SCB_HFSR_FORCED_Msk [6/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 685 of file core_cm4.h.

◆ SCB_HFSR_FORCED_Msk [7/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 738 of file core_cm7.h.

◆ SCB_HFSR_FORCED_Msk [8/8]

#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)

SCB HFSR: FORCED Mask

Definition at line 618 of file core_sc300.h.

◆ SCB_HFSR_FORCED_Pos [1/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 816 of file core_armv81mml.h.

◆ SCB_HFSR_FORCED_Pos [2/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 807 of file core_armv8mml.h.

◆ SCB_HFSR_FORCED_Pos [3/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 620 of file core_cm3.h.

◆ SCB_HFSR_FORCED_Pos [4/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 807 of file core_cm33.h.

◆ SCB_HFSR_FORCED_Pos [5/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 807 of file core_cm35p.h.

◆ SCB_HFSR_FORCED_Pos [6/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 684 of file core_cm4.h.

◆ SCB_HFSR_FORCED_Pos [7/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 737 of file core_cm7.h.

◆ SCB_HFSR_FORCED_Pos [8/8]

#define SCB_HFSR_FORCED_Pos 30U

SCB HFSR: FORCED Position

Definition at line 617 of file core_sc300.h.

◆ SCB_HFSR_VECTTBL_Msk [1/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 820 of file core_armv81mml.h.

◆ SCB_HFSR_VECTTBL_Msk [2/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 811 of file core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Msk [3/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 624 of file core_cm3.h.

◆ SCB_HFSR_VECTTBL_Msk [4/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 811 of file core_cm33.h.

◆ SCB_HFSR_VECTTBL_Msk [5/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 811 of file core_cm35p.h.

◆ SCB_HFSR_VECTTBL_Msk [6/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 688 of file core_cm4.h.

◆ SCB_HFSR_VECTTBL_Msk [7/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 741 of file core_cm7.h.

◆ SCB_HFSR_VECTTBL_Msk [8/8]

#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)

SCB HFSR: VECTTBL Mask

Definition at line 621 of file core_sc300.h.

◆ SCB_HFSR_VECTTBL_Pos [1/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 819 of file core_armv81mml.h.

◆ SCB_HFSR_VECTTBL_Pos [2/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 810 of file core_armv8mml.h.

◆ SCB_HFSR_VECTTBL_Pos [3/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 623 of file core_cm3.h.

◆ SCB_HFSR_VECTTBL_Pos [4/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 810 of file core_cm33.h.

◆ SCB_HFSR_VECTTBL_Pos [5/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 810 of file core_cm35p.h.

◆ SCB_HFSR_VECTTBL_Pos [6/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 687 of file core_cm4.h.

◆ SCB_HFSR_VECTTBL_Pos [7/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 740 of file core_cm7.h.

◆ SCB_HFSR_VECTTBL_Pos [8/8]

#define SCB_HFSR_VECTTBL_Pos 1U

SCB HFSR: VECTTBL Position

Definition at line 620 of file core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Msk [1/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 597 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [2/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Msk [3/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 588 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Msk [4/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Msk [5/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 408 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Msk [6/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 390 of file core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Msk [7/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 443 of file core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Msk [8/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 435 of file core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Msk [9/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 588 of file core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Msk [10/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 588 of file core_cm35p.h.

◆ SCB_ICSR_ISRPENDING_Msk [11/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 501 of file core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Msk [12/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 545 of file core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Msk [13/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 398 of file core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Msk [14/14]

#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)

SCB ICSR: ISRPENDING Mask

Definition at line 437 of file core_sc300.h.

◆ SCB_ICSR_ISRPENDING_Pos [1/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 596 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [2/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPENDING_Pos [3/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 587 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPENDING_Pos [4/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file core_cm0.h.

◆ SCB_ICSR_ISRPENDING_Pos [5/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 407 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPENDING_Pos [6/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 389 of file core_cm1.h.

◆ SCB_ICSR_ISRPENDING_Pos [7/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 442 of file core_cm23.h.

◆ SCB_ICSR_ISRPENDING_Pos [8/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 434 of file core_cm3.h.

◆ SCB_ICSR_ISRPENDING_Pos [9/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 587 of file core_cm33.h.

◆ SCB_ICSR_ISRPENDING_Pos [10/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 587 of file core_cm35p.h.

◆ SCB_ICSR_ISRPENDING_Pos [11/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 500 of file core_cm4.h.

◆ SCB_ICSR_ISRPENDING_Pos [12/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 544 of file core_cm7.h.

◆ SCB_ICSR_ISRPENDING_Pos [13/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 397 of file core_sc000.h.

◆ SCB_ICSR_ISRPENDING_Pos [14/14]

#define SCB_ICSR_ISRPENDING_Pos 22U

SCB ICSR: ISRPENDING Position

Definition at line 436 of file core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [1/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 594 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [2/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [3/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 585 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [4/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [5/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 405 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [6/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 387 of file core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [7/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 440 of file core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [8/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 432 of file core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [9/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 585 of file core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [10/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 585 of file core_cm35p.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [11/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 498 of file core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [12/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 542 of file core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [13/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 395 of file core_sc000.h.

◆ SCB_ICSR_ISRPREEMPT_Msk [14/14]

#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)

SCB ICSR: ISRPREEMPT Mask

Definition at line 434 of file core_sc300.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [1/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 593 of file core_armv81mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [2/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file core_armv8mbl.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [3/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 584 of file core_armv8mml.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [4/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file core_cm0.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [5/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 404 of file core_cm0plus.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [6/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 386 of file core_cm1.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [7/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 439 of file core_cm23.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [8/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 431 of file core_cm3.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [9/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 584 of file core_cm33.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [10/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 584 of file core_cm35p.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [11/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 497 of file core_cm4.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [12/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 541 of file core_cm7.h.

◆ SCB_ICSR_ISRPREEMPT_Pos [13/14]

#define SCB_ICSR_ISRPREEMPT_Pos 23U

SCB ICSR: ISRPREEMPT Position

Definition at line 394 of file core_sc000.h.

#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk

#define SCB_ICSR_NMIPENDSET_Pos 31U

SCB ICSR: NMIPENDSET Position

Definition at line 526 of file core_cm7.h.

◆ SCB_ICSR_NMIPENDSET_Pos [13/14]

#define SCB_ICSR_NMIPENDSET_Pos 31U

SCB ICSR: NMIPENDSET Position

Definition at line 379 of file core_sc000.h.

◆ SCB_ICSR_NMIPENDSET_Pos [14/14]

#define SCB_ICSR_NMIPENDSET_Pos 31U

SCB ICSR: NMIPENDSET Position

Definition at line 418 of file core_sc300.h.

◆ SCB_ICSR_PENDNMICLR_Msk [1/6]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 576 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [2/6]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Msk [3/6]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 567 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Msk [4/6]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 422 of file core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Msk [5/6]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 567 of file core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Msk [6/6]

#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)

SCB ICSR: PENDNMICLR Mask

Definition at line 567 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMICLR_Pos [1/6]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 575 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [2/6]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMICLR_Pos [3/6]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 566 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMICLR_Pos [4/6]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 421 of file core_cm23.h.

◆ SCB_ICSR_PENDNMICLR_Pos [5/6]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 566 of file core_cm33.h.

◆ SCB_ICSR_PENDNMICLR_Pos [6/6]

#define SCB_ICSR_PENDNMICLR_Pos 30U

SCB ICSR: PENDNMICLR Position

Definition at line 566 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMISET_Msk [1/6]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 570 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [2/6]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Msk [3/6]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 561 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Msk [4/6]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 416 of file core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Msk [5/6]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 561 of file core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Msk [6/6]

#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)

SCB ICSR: PENDNMISET Mask

Definition at line 561 of file core_cm35p.h.

◆ SCB_ICSR_PENDNMISET_Pos [1/6]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 569 of file core_armv81mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [2/6]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDNMISET_Pos [3/6]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 560 of file core_armv8mml.h.

◆ SCB_ICSR_PENDNMISET_Pos [4/6]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 415 of file core_cm23.h.

◆ SCB_ICSR_PENDNMISET_Pos [5/6]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 560 of file core_cm33.h.

◆ SCB_ICSR_PENDNMISET_Pos [6/6]

#define SCB_ICSR_PENDNMISET_Pos 31U

SCB ICSR: PENDNMISET Position

Definition at line 560 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTCLR_Msk [1/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 588 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [2/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Msk [3/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 579 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Msk [4/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Msk [5/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 402 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Msk [6/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 384 of file core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Msk [7/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 434 of file core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Msk [8/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 429 of file core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Msk [9/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 579 of file core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Msk [10/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 579 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTCLR_Msk [11/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 495 of file core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Msk [12/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 539 of file core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Msk [13/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 392 of file core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Msk [14/14]

#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)

SCB ICSR: PENDSTCLR Mask

Definition at line 431 of file core_sc300.h.

◆ SCB_ICSR_PENDSTCLR_Pos [1/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 587 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [2/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTCLR_Pos [3/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 578 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTCLR_Pos [4/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file core_cm0.h.

◆ SCB_ICSR_PENDSTCLR_Pos [5/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 401 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTCLR_Pos [6/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 383 of file core_cm1.h.

◆ SCB_ICSR_PENDSTCLR_Pos [7/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 433 of file core_cm23.h.

◆ SCB_ICSR_PENDSTCLR_Pos [8/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 428 of file core_cm3.h.

◆ SCB_ICSR_PENDSTCLR_Pos [9/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 578 of file core_cm33.h.

◆ SCB_ICSR_PENDSTCLR_Pos [10/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 578 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTCLR_Pos [11/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 494 of file core_cm4.h.

◆ SCB_ICSR_PENDSTCLR_Pos [12/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 538 of file core_cm7.h.

◆ SCB_ICSR_PENDSTCLR_Pos [13/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 391 of file core_sc000.h.

◆ SCB_ICSR_PENDSTCLR_Pos [14/14]

#define SCB_ICSR_PENDSTCLR_Pos 25U

SCB ICSR: PENDSTCLR Position

Definition at line 430 of file core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Msk [1/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 585 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [2/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Msk [3/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 576 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Msk [4/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Msk [5/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 399 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Msk [6/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 381 of file core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Msk [7/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 431 of file core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Msk [8/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 426 of file core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Msk [9/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 576 of file core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Msk [10/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 576 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTSET_Msk [11/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 492 of file core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Msk [12/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 536 of file core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Msk [13/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 389 of file core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Msk [14/14]

#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)

SCB ICSR: PENDSTSET Mask

Definition at line 428 of file core_sc300.h.

◆ SCB_ICSR_PENDSTSET_Pos [1/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 584 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [2/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSTSET_Pos [3/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 575 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSTSET_Pos [4/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file core_cm0.h.

◆ SCB_ICSR_PENDSTSET_Pos [5/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 398 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSTSET_Pos [6/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 380 of file core_cm1.h.

◆ SCB_ICSR_PENDSTSET_Pos [7/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 430 of file core_cm23.h.

◆ SCB_ICSR_PENDSTSET_Pos [8/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 425 of file core_cm3.h.

◆ SCB_ICSR_PENDSTSET_Pos [9/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 575 of file core_cm33.h.

◆ SCB_ICSR_PENDSTSET_Pos [10/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 575 of file core_cm35p.h.

◆ SCB_ICSR_PENDSTSET_Pos [11/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 491 of file core_cm4.h.

◆ SCB_ICSR_PENDSTSET_Pos [12/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 535 of file core_cm7.h.

◆ SCB_ICSR_PENDSTSET_Pos [13/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 388 of file core_sc000.h.

◆ SCB_ICSR_PENDSTSET_Pos [14/14]

#define SCB_ICSR_PENDSTSET_Pos 26U

SCB ICSR: PENDSTSET Position

Definition at line 427 of file core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Msk [1/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 582 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [2/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Msk [3/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 573 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Msk [4/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Msk [5/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 396 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Msk [6/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 378 of file core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Msk [7/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 428 of file core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Msk [8/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 423 of file core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Msk [9/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 573 of file core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Msk [10/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 573 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVCLR_Msk [11/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 489 of file core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Msk [12/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 533 of file core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Msk [13/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 386 of file core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Msk [14/14]

#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)

SCB ICSR: PENDSVCLR Mask

Definition at line 425 of file core_sc300.h.

◆ SCB_ICSR_PENDSVCLR_Pos [1/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 581 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [2/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVCLR_Pos [3/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 572 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVCLR_Pos [4/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file core_cm0.h.

◆ SCB_ICSR_PENDSVCLR_Pos [5/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 395 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVCLR_Pos [6/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 377 of file core_cm1.h.

◆ SCB_ICSR_PENDSVCLR_Pos [7/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 427 of file core_cm23.h.

◆ SCB_ICSR_PENDSVCLR_Pos [8/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 422 of file core_cm3.h.

◆ SCB_ICSR_PENDSVCLR_Pos [9/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 572 of file core_cm33.h.

◆ SCB_ICSR_PENDSVCLR_Pos [10/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 572 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVCLR_Pos [11/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 488 of file core_cm4.h.

◆ SCB_ICSR_PENDSVCLR_Pos [12/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 532 of file core_cm7.h.

◆ SCB_ICSR_PENDSVCLR_Pos [13/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 385 of file core_sc000.h.

◆ SCB_ICSR_PENDSVCLR_Pos [14/14]

#define SCB_ICSR_PENDSVCLR_Pos 27U

SCB ICSR: PENDSVCLR Position

Definition at line 424 of file core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Msk [1/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 579 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [2/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Msk [3/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 570 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Msk [4/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Msk [5/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 393 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Msk [6/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 375 of file core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Msk [7/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 425 of file core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Msk [8/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 420 of file core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Msk [9/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 570 of file core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Msk [10/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 570 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVSET_Msk [11/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 486 of file core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Msk [12/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 530 of file core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Msk [13/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 383 of file core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Msk [14/14]

#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)

SCB ICSR: PENDSVSET Mask

Definition at line 422 of file core_sc300.h.

◆ SCB_ICSR_PENDSVSET_Pos [1/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 578 of file core_armv81mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [2/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file core_armv8mbl.h.

◆ SCB_ICSR_PENDSVSET_Pos [3/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 569 of file core_armv8mml.h.

◆ SCB_ICSR_PENDSVSET_Pos [4/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file core_cm0.h.

◆ SCB_ICSR_PENDSVSET_Pos [5/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 392 of file core_cm0plus.h.

◆ SCB_ICSR_PENDSVSET_Pos [6/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 374 of file core_cm1.h.

◆ SCB_ICSR_PENDSVSET_Pos [7/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 424 of file core_cm23.h.

◆ SCB_ICSR_PENDSVSET_Pos [8/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 419 of file core_cm3.h.

◆ SCB_ICSR_PENDSVSET_Pos [9/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 569 of file core_cm33.h.

◆ SCB_ICSR_PENDSVSET_Pos [10/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 569 of file core_cm35p.h.

◆ SCB_ICSR_PENDSVSET_Pos [11/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 485 of file core_cm4.h.

◆ SCB_ICSR_PENDSVSET_Pos [12/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 529 of file core_cm7.h.

◆ SCB_ICSR_PENDSVSET_Pos [13/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 382 of file core_sc000.h.

◆ SCB_ICSR_PENDSVSET_Pos [14/14]

#define SCB_ICSR_PENDSVSET_Pos 28U

SCB ICSR: PENDSVSET Position

Definition at line 421 of file core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Msk [1/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 603 of file core_armv81mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [2/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Msk [3/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 594 of file core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Msk [4/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 449 of file core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Msk [5/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 441 of file core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Msk [6/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 594 of file core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Msk [7/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 594 of file core_cm35p.h.

◆ SCB_ICSR_RETTOBASE_Msk [8/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 507 of file core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Msk [9/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 551 of file core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Msk [10/10]

#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)

SCB ICSR: RETTOBASE Mask

Definition at line 443 of file core_sc300.h.

◆ SCB_ICSR_RETTOBASE_Pos [1/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 602 of file core_armv81mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [2/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file core_armv8mbl.h.

◆ SCB_ICSR_RETTOBASE_Pos [3/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 593 of file core_armv8mml.h.

◆ SCB_ICSR_RETTOBASE_Pos [4/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 448 of file core_cm23.h.

◆ SCB_ICSR_RETTOBASE_Pos [5/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 440 of file core_cm3.h.

◆ SCB_ICSR_RETTOBASE_Pos [6/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 593 of file core_cm33.h.

◆ SCB_ICSR_RETTOBASE_Pos [7/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 593 of file core_cm35p.h.

◆ SCB_ICSR_RETTOBASE_Pos [8/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 506 of file core_cm4.h.

◆ SCB_ICSR_RETTOBASE_Pos [9/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 550 of file core_cm7.h.

◆ SCB_ICSR_RETTOBASE_Pos [10/10]

#define SCB_ICSR_RETTOBASE_Pos 11U

SCB ICSR: RETTOBASE Position

Definition at line 442 of file core_sc300.h.

◆ SCB_ICSR_STTNS_Msk [1/6]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 591 of file core_armv81mml.h.

◆ SCB_ICSR_STTNS_Msk [2/6]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Msk [3/6]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 582 of file core_armv8mml.h.

◆ SCB_ICSR_STTNS_Msk [4/6]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 437 of file core_cm23.h.

◆ SCB_ICSR_STTNS_Msk [5/6]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 582 of file core_cm33.h.

◆ SCB_ICSR_STTNS_Msk [6/6]

#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)

SCB ICSR: STTNS Mask (Security Extension)

Definition at line 582 of file core_cm35p.h.

◆ SCB_ICSR_STTNS_Pos [1/6]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 590 of file core_armv81mml.h.

◆ SCB_ICSR_STTNS_Pos [2/6]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file core_armv8mbl.h.

◆ SCB_ICSR_STTNS_Pos [3/6]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 581 of file core_armv8mml.h.

◆ SCB_ICSR_STTNS_Pos [4/6]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 436 of file core_cm23.h.

◆ SCB_ICSR_STTNS_Pos [5/6]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 581 of file core_cm33.h.

◆ SCB_ICSR_STTNS_Pos [6/6]

#define SCB_ICSR_STTNS_Pos 24U

SCB ICSR: STTNS Position (Security Extension)

Definition at line 581 of file core_cm35p.h.

◆ SCB_ICSR_VECTACTIVE_Msk [1/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 606 of file core_armv81mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [2/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Msk [3/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 597 of file core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Msk [4/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Msk [5/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 414 of file core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Msk [6/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 396 of file core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Msk [7/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 452 of file core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Msk [8/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 444 of file core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Msk [9/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 597 of file core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Msk [10/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 597 of file core_cm35p.h.

◆ SCB_ICSR_VECTACTIVE_Msk [11/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 510 of file core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Msk [12/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 554 of file core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Msk [13/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 404 of file core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Msk [14/14]

#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)

SCB ICSR: VECTACTIVE Mask

Definition at line 446 of file core_sc300.h.

◆ SCB_ICSR_VECTACTIVE_Pos [1/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 605 of file core_armv81mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [2/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTACTIVE_Pos [3/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 596 of file core_armv8mml.h.

◆ SCB_ICSR_VECTACTIVE_Pos [4/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file core_cm0.h.

◆ SCB_ICSR_VECTACTIVE_Pos [5/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 413 of file core_cm0plus.h.

◆ SCB_ICSR_VECTACTIVE_Pos [6/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 395 of file core_cm1.h.

◆ SCB_ICSR_VECTACTIVE_Pos [7/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 451 of file core_cm23.h.

◆ SCB_ICSR_VECTACTIVE_Pos [8/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 443 of file core_cm3.h.

◆ SCB_ICSR_VECTACTIVE_Pos [9/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 596 of file core_cm33.h.

◆ SCB_ICSR_VECTACTIVE_Pos [10/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 596 of file core_cm35p.h.

◆ SCB_ICSR_VECTACTIVE_Pos [11/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 509 of file core_cm4.h.

◆ SCB_ICSR_VECTACTIVE_Pos [12/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 553 of file core_cm7.h.

◆ SCB_ICSR_VECTACTIVE_Pos [13/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 403 of file core_sc000.h.

◆ SCB_ICSR_VECTACTIVE_Pos [14/14]

#define SCB_ICSR_VECTACTIVE_Pos 0U

SCB ICSR: VECTACTIVE Position

Definition at line 445 of file core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Msk [1/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 600 of file core_armv81mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [2/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Msk [3/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 591 of file core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Msk [4/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Msk [5/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 411 of file core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Msk [6/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 393 of file core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Msk [7/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 446 of file core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Msk [8/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 438 of file core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Msk [9/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 591 of file core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Msk [10/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 591 of file core_cm35p.h.

◆ SCB_ICSR_VECTPENDING_Msk [11/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 504 of file core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Msk [12/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 548 of file core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Msk [13/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 401 of file core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Msk [14/14]

#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)

SCB ICSR: VECTPENDING Mask

Definition at line 440 of file core_sc300.h.

◆ SCB_ICSR_VECTPENDING_Pos [1/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 599 of file core_armv81mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [2/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file core_armv8mbl.h.

◆ SCB_ICSR_VECTPENDING_Pos [3/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 590 of file core_armv8mml.h.

◆ SCB_ICSR_VECTPENDING_Pos [4/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file core_cm0.h.

◆ SCB_ICSR_VECTPENDING_Pos [5/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 410 of file core_cm0plus.h.

◆ SCB_ICSR_VECTPENDING_Pos [6/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 392 of file core_cm1.h.

◆ SCB_ICSR_VECTPENDING_Pos [7/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 445 of file core_cm23.h.

◆ SCB_ICSR_VECTPENDING_Pos [8/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 437 of file core_cm3.h.

◆ SCB_ICSR_VECTPENDING_Pos [9/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 590 of file core_cm33.h.

◆ SCB_ICSR_VECTPENDING_Pos [10/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 590 of file core_cm35p.h.

◆ SCB_ICSR_VECTPENDING_Pos [11/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 503 of file core_cm4.h.

◆ SCB_ICSR_VECTPENDING_Pos [12/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 547 of file core_cm7.h.

◆ SCB_ICSR_VECTPENDING_Pos [13/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 400 of file core_sc000.h.

◆ SCB_ICSR_VECTPENDING_Pos [14/14]

#define SCB_ICSR_VECTPENDING_Pos 12U

SCB ICSR: VECTPENDING Position

Definition at line 439 of file core_sc300.h.

◆ SCB_ITCMCR_EN_Msk [1/2]

#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 936 of file core_armv81mml.h.

◆ SCB_ITCMCR_EN_Msk [2/2]

#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)

SCB ITCMCR: EN Mask

Definition at line 847 of file core_cm7.h.

◆ SCB_ITCMCR_EN_Pos [1/2]

#define SCB_ITCMCR_EN_Pos 0U

SCB ITCMCR: EN Position

Definition at line 935 of file core_armv81mml.h.

◆ SCB_ITCMCR_EN_Pos [2/2]

#define SCB_ITCMCR_EN_Pos 0U

SCB ITCMCR: EN Position

Definition at line 846 of file core_cm7.h.

◆ SCB_ITCMCR_RETEN_Msk [1/2]

#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 930 of file core_armv81mml.h.

◆ SCB_ITCMCR_RETEN_Msk [2/2]

#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)

SCB ITCMCR: RETEN Mask

Definition at line 841 of file core_cm7.h.

◆ SCB_ITCMCR_RETEN_Pos [1/2]

#define SCB_ITCMCR_RETEN_Pos 2U

SCB ITCMCR: RETEN Position

Definition at line 929 of file core_armv81mml.h.

◆ SCB_ITCMCR_RETEN_Pos [2/2]

#define SCB_ITCMCR_RETEN_Pos 2U

SCB ITCMCR: RETEN Position

Definition at line 840 of file core_cm7.h.

◆ SCB_ITCMCR_RMW_Msk [1/2]

#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 933 of file core_armv81mml.h.

◆ SCB_ITCMCR_RMW_Msk [2/2]

#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)

SCB ITCMCR: RMW Mask

Definition at line 844 of file core_cm7.h.

◆ SCB_ITCMCR_RMW_Pos [1/2]

#define SCB_ITCMCR_RMW_Pos 1U

SCB ITCMCR: RMW Position

Definition at line 932 of file core_armv81mml.h.

◆ SCB_ITCMCR_RMW_Pos [2/2]

#define SCB_ITCMCR_RMW_Pos 1U

SCB ITCMCR: RMW Position

Definition at line 843 of file core_cm7.h.

◆ SCB_ITCMCR_SZ_Msk [1/2]

#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 927 of file core_armv81mml.h.

◆ SCB_ITCMCR_SZ_Msk [2/2]

#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)

SCB ITCMCR: SZ Mask

Definition at line 838 of file core_cm7.h.

◆ SCB_ITCMCR_SZ_Pos [1/2]

#define SCB_ITCMCR_SZ_Pos 3U

SCB ITCMCR: SZ Position

Definition at line 926 of file core_armv81mml.h.

◆ SCB_ITCMCR_SZ_Pos [2/2]

#define SCB_ITCMCR_SZ_Pos 3U

SCB ITCMCR: SZ Position

Definition at line 837 of file core_cm7.h.

◆ SCB_NSACR_CP10_Msk [1/4]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 843 of file core_armv81mml.h.

◆ SCB_NSACR_CP10_Msk [2/4]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 834 of file core_armv8mml.h.

◆ SCB_NSACR_CP10_Msk [3/4]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 834 of file core_cm33.h.

◆ SCB_NSACR_CP10_Msk [4/4]

#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)

SCB NSACR: CP10 Mask

Definition at line 834 of file core_cm35p.h.

◆ SCB_NSACR_CP10_Pos [1/4]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

Definition at line 842 of file core_armv81mml.h.

◆ SCB_NSACR_CP10_Pos [2/4]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

Definition at line 833 of file core_armv8mml.h.

◆ SCB_NSACR_CP10_Pos [3/4]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

Definition at line 833 of file core_cm33.h.

◆ SCB_NSACR_CP10_Pos [4/4]

#define SCB_NSACR_CP10_Pos 10U

SCB NSACR: CP10 Position

Definition at line 833 of file core_cm35p.h.

◆ SCB_NSACR_CP11_Msk [1/4]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 840 of file core_armv81mml.h.

◆ SCB_NSACR_CP11_Msk [2/4]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 831 of file core_armv8mml.h.

◆ SCB_NSACR_CP11_Msk [3/4]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 831 of file core_cm33.h.

◆ SCB_NSACR_CP11_Msk [4/4]

#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)

SCB NSACR: CP11 Mask

Definition at line 831 of file core_cm35p.h.

◆ SCB_NSACR_CP11_Pos [1/4]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

Definition at line 839 of file core_armv81mml.h.

◆ SCB_NSACR_CP11_Pos [2/4]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

Definition at line 830 of file core_armv8mml.h.

◆ SCB_NSACR_CP11_Pos [3/4]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

Definition at line 830 of file core_cm33.h.

◆ SCB_NSACR_CP11_Pos [4/4]

#define SCB_NSACR_CP11_Pos 11U

SCB NSACR: CP11 Position

Definition at line 830 of file core_cm35p.h.

◆ SCB_NSACR_CPn_Msk [1/4]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 846 of file core_armv81mml.h.

◆ SCB_NSACR_CPn_Msk [2/4]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 837 of file core_armv8mml.h.

◆ SCB_NSACR_CPn_Msk [3/4]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 837 of file core_cm33.h.

◆ SCB_NSACR_CPn_Msk [4/4]

#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)

SCB NSACR: CPn Mask

Definition at line 837 of file core_cm35p.h.

◆ SCB_NSACR_CPn_Pos [1/4]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

Definition at line 845 of file core_armv81mml.h.

◆ SCB_NSACR_CPn_Pos [2/4]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

Definition at line 836 of file core_armv8mml.h.

◆ SCB_NSACR_CPn_Pos [3/4]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

Definition at line 836 of file core_cm33.h.

◆ SCB_NSACR_CPn_Pos [4/4]

#define SCB_NSACR_CPn_Pos 0U

SCB NSACR: CPn Position

Definition at line 836 of file core_cm35p.h.

◆ SCB_SCR_SEVONPEND_Msk [1/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 642 of file core_armv81mml.h.

◆ SCB_SCR_SEVONPEND_Msk [2/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Msk [3/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 633 of file core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Msk [4/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file core_cm0.h.

◆ SCB_SCR_SEVONPEND_Msk [5/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 440 of file core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Msk [6/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 416 of file core_cm1.h.

◆ SCB_SCR_SEVONPEND_Msk [7/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 487 of file core_cm23.h.

◆ SCB_SCR_SEVONPEND_Msk [8/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 482 of file core_cm3.h.

◆ SCB_SCR_SEVONPEND_Msk [9/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 633 of file core_cm33.h.

◆ SCB_SCR_SEVONPEND_Msk [10/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 633 of file core_cm35p.h.

◆ SCB_SCR_SEVONPEND_Msk [11/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 540 of file core_cm4.h.

◆ SCB_SCR_SEVONPEND_Msk [12/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 584 of file core_cm7.h.

◆ SCB_SCR_SEVONPEND_Msk [13/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 428 of file core_sc000.h.

◆ SCB_SCR_SEVONPEND_Msk [14/14]

#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)

SCB SCR: SEVONPEND Mask

Definition at line 479 of file core_sc300.h.

◆ SCB_SCR_SEVONPEND_Pos [1/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 641 of file core_armv81mml.h.

◆ SCB_SCR_SEVONPEND_Pos [2/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file core_armv8mbl.h.

◆ SCB_SCR_SEVONPEND_Pos [3/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 632 of file core_armv8mml.h.

◆ SCB_SCR_SEVONPEND_Pos [4/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file core_cm0.h.

◆ SCB_SCR_SEVONPEND_Pos [5/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 439 of file core_cm0plus.h.

◆ SCB_SCR_SEVONPEND_Pos [6/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 415 of file core_cm1.h.

◆ SCB_SCR_SEVONPEND_Pos [7/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 486 of file core_cm23.h.

◆ SCB_SCR_SEVONPEND_Pos [8/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 481 of file core_cm3.h.

◆ SCB_SCR_SEVONPEND_Pos [9/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 632 of file core_cm33.h.

◆ SCB_SCR_SEVONPEND_Pos [10/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 632 of file core_cm35p.h.

◆ SCB_SCR_SEVONPEND_Pos [11/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 539 of file core_cm4.h.

◆ SCB_SCR_SEVONPEND_Pos [12/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 583 of file core_cm7.h.

◆ SCB_SCR_SEVONPEND_Pos [13/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 427 of file core_sc000.h.

◆ SCB_SCR_SEVONPEND_Pos [14/14]

#define SCB_SCR_SEVONPEND_Pos 4U

SCB SCR: SEVONPEND Position

Definition at line 478 of file core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Msk [1/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 648 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [2/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Msk [3/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 639 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Msk [4/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Msk [5/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 443 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Msk [6/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 419 of file core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Msk [7/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 493 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Msk [8/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 485 of file core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Msk [9/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 639 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Msk [10/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 639 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEP_Msk [11/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 543 of file core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Msk [12/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 587 of file core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Msk [13/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 431 of file core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Msk [14/14]

#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)

SCB SCR: SLEEPDEEP Mask

Definition at line 482 of file core_sc300.h.

◆ SCB_SCR_SLEEPDEEP_Pos [1/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 647 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [2/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEP_Pos [3/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 638 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEP_Pos [4/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file core_cm0.h.

◆ SCB_SCR_SLEEPDEEP_Pos [5/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 442 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPDEEP_Pos [6/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 418 of file core_cm1.h.

◆ SCB_SCR_SLEEPDEEP_Pos [7/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 492 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEP_Pos [8/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 484 of file core_cm3.h.

◆ SCB_SCR_SLEEPDEEP_Pos [9/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 638 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEP_Pos [10/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 638 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEP_Pos [11/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 542 of file core_cm4.h.

◆ SCB_SCR_SLEEPDEEP_Pos [12/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 586 of file core_cm7.h.

◆ SCB_SCR_SLEEPDEEP_Pos [13/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 430 of file core_sc000.h.

◆ SCB_SCR_SLEEPDEEP_Pos [14/14]

#define SCB_SCR_SLEEPDEEP_Pos 2U

SCB SCR: SLEEPDEEP Position

Definition at line 481 of file core_sc300.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [1/6]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 645 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [2/6]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [3/6]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 636 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [4/6]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 490 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [5/6]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 636 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Msk [6/6]

#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)

SCB SCR: SLEEPDEEPS Mask

Definition at line 636 of file core_cm35p.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [1/6]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 644 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [2/6]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [3/6]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 635 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [4/6]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 489 of file core_cm23.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [5/6]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 635 of file core_cm33.h.

◆ SCB_SCR_SLEEPDEEPS_Pos [6/6]

#define SCB_SCR_SLEEPDEEPS_Pos 3U

SCB SCR: SLEEPDEEPS Position

Definition at line 635 of file core_cm35p.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [1/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 651 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [2/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [3/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 642 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [4/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [5/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 446 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [6/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 422 of file core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [7/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 496 of file core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [8/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 488 of file core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [9/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 642 of file core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [10/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 642 of file core_cm35p.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [11/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 546 of file core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [12/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 590 of file core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [13/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 434 of file core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Msk [14/14]

#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)

SCB SCR: SLEEPONEXIT Mask

Definition at line 485 of file core_sc300.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [1/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 650 of file core_armv81mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [2/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file core_armv8mbl.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [3/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 641 of file core_armv8mml.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [4/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file core_cm0.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [5/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 445 of file core_cm0plus.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [6/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 421 of file core_cm1.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [7/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 495 of file core_cm23.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [8/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 487 of file core_cm3.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [9/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 641 of file core_cm33.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [10/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 641 of file core_cm35p.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [11/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 545 of file core_cm4.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [12/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 589 of file core_cm7.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [13/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 433 of file core_sc000.h.

◆ SCB_SCR_SLEEPONEXIT_Pos [14/14]

#define SCB_SCR_SLEEPONEXIT_Pos 1U

SCB SCR: SLEEPONEXIT Position

Definition at line 484 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [1/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 734 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [2/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 725 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [3/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 547 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [4/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 725 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [5/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 725 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [6/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 605 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [7/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 658 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Msk [8/8]

#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)

SCB SHCSR: BUSFAULTACT Mask

Definition at line 544 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [1/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 733 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [2/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 724 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [3/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 546 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [4/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 724 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [5/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 724 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [6/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 604 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [7/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 657 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTACT_Pos [8/8]

#define SCB_SHCSR_BUSFAULTACT_Pos 1U

SCB SHCSR: BUSFAULTACT Position

Definition at line 543 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [1/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 692 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [2/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 683 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [3/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 514 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [4/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 683 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [5/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 683 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [6/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 572 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [7/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 625 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Msk [8/8]

#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)

SCB SHCSR: BUSFAULTENA Mask

Definition at line 511 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [1/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 691 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [2/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 682 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [3/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 513 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [4/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 682 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [5/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 682 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [6/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 571 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [7/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 624 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTENA_Pos [8/8]

#define SCB_SHCSR_BUSFAULTENA_Pos 17U

SCB SHCSR: BUSFAULTENA Position

Definition at line 510 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [1/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 701 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [2/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 692 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [3/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 523 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [4/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 692 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [5/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 692 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [6/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 581 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [7/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 634 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Msk [8/8]

#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)

SCB SHCSR: BUSFAULTPENDED Mask

Definition at line 520 of file core_sc300.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [1/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 700 of file core_armv81mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [2/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 691 of file core_armv8mml.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [3/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 522 of file core_cm3.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [4/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 691 of file core_cm33.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [5/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 691 of file core_cm35p.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [6/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 580 of file core_cm4.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [7/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 633 of file core_cm7.h.

◆ SCB_SHCSR_BUSFAULTPENDED_Pos [8/8]

#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U

SCB SHCSR: BUSFAULTPENDED Position

Definition at line 519 of file core_sc300.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [1/6]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 731 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [2/6]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [3/6]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 722 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [4/6]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 543 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [5/6]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 722 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Msk [6/6]

#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)

SCB SHCSR: HARDFAULTACT Mask

Definition at line 722 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [1/6]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 730 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [2/6]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [3/6]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 721 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [4/6]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 542 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [5/6]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 721 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTACT_Pos [6/6]

#define SCB_SHCSR_HARDFAULTACT_Pos 2U

SCB SHCSR: HARDFAULTACT Position

Definition at line 721 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [1/6]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 680 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [2/6]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [3/6]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 671 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [4/6]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 525 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [5/6]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 671 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Msk [6/6]

#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)

SCB SHCSR: HARDFAULTPENDED Mask

Definition at line 671 of file core_cm35p.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [1/6]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 679 of file core_armv81mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [2/6]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file core_armv8mbl.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [3/6]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 670 of file core_armv8mml.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [4/6]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 524 of file core_cm23.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [5/6]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 670 of file core_cm33.h.

◆ SCB_SHCSR_HARDFAULTPENDED_Pos [6/6]

#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U

SCB SHCSR: HARDFAULTPENDED Position

Definition at line 670 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [1/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 737 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [2/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 728 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [3/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 550 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [4/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 728 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [5/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 728 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [6/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 608 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [7/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 661 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Msk [8/8]

#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)

SCB SHCSR: MEMFAULTACT Mask

Definition at line 547 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [1/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 736 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [2/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 727 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [3/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 549 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [4/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 727 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [5/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 727 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [6/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 607 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [7/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 660 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTACT_Pos [8/8]

#define SCB_SHCSR_MEMFAULTACT_Pos 0U

SCB SHCSR: MEMFAULTACT Position

Definition at line 546 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [1/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 695 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [2/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 686 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [3/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 517 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [4/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 686 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [5/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 686 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [6/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 575 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [7/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 628 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Msk [8/8]

#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)

SCB SHCSR: MEMFAULTENA Mask

Definition at line 514 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [1/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 694 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [2/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 685 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [3/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 516 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [4/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 685 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [5/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 685 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [6/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 574 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [7/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 627 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTENA_Pos [8/8]

#define SCB_SHCSR_MEMFAULTENA_Pos 16U

SCB SHCSR: MEMFAULTENA Position

Definition at line 513 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [1/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 704 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [2/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 695 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [3/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 526 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [4/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 695 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [5/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 695 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [6/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 584 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [7/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 637 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Msk [8/8]

#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)

SCB SHCSR: MEMFAULTPENDED Mask

Definition at line 523 of file core_sc300.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [1/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 703 of file core_armv81mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [2/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 694 of file core_armv8mml.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [3/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 525 of file core_cm3.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [4/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 694 of file core_cm33.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [5/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 694 of file core_cm35p.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [6/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 583 of file core_cm4.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [7/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 636 of file core_cm7.h.

◆ SCB_SHCSR_MEMFAULTPENDED_Pos [8/8]

#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U

SCB SHCSR: MEMFAULTPENDED Position

Definition at line 522 of file core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Msk [1/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 716 of file core_armv81mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [2/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 707 of file core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Msk [3/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 538 of file core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Msk [4/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 707 of file core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Msk [5/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 707 of file core_cm35p.h.

◆ SCB_SHCSR_MONITORACT_Msk [6/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 596 of file core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Msk [7/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 649 of file core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Msk [8/8]

#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)

SCB SHCSR: MONITORACT Mask

Definition at line 535 of file core_sc300.h.

◆ SCB_SHCSR_MONITORACT_Pos [1/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 715 of file core_armv81mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [2/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 706 of file core_armv8mml.h.

◆ SCB_SHCSR_MONITORACT_Pos [3/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 537 of file core_cm3.h.

◆ SCB_SHCSR_MONITORACT_Pos [4/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 706 of file core_cm33.h.

◆ SCB_SHCSR_MONITORACT_Pos [5/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 706 of file core_cm35p.h.

◆ SCB_SHCSR_MONITORACT_Pos [6/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 595 of file core_cm4.h.

◆ SCB_SHCSR_MONITORACT_Pos [7/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 648 of file core_cm7.h.

◆ SCB_SHCSR_MONITORACT_Pos [8/8]

#define SCB_SHCSR_MONITORACT_Pos 8U

SCB SHCSR: MONITORACT Position

Definition at line 534 of file core_sc300.h.

◆ SCB_SHCSR_NMIACT_Msk [1/6]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 722 of file core_armv81mml.h.

◆ SCB_SHCSR_NMIACT_Msk [2/6]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Msk [3/6]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 713 of file core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Msk [4/6]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 540 of file core_cm23.h.

◆ SCB_SHCSR_NMIACT_Msk [5/6]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 713 of file core_cm33.h.

◆ SCB_SHCSR_NMIACT_Msk [6/6]

#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)

SCB SHCSR: NMIACT Mask

Definition at line 713 of file core_cm35p.h.

◆ SCB_SHCSR_NMIACT_Pos [1/6]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 721 of file core_armv81mml.h.

◆ SCB_SHCSR_NMIACT_Pos [2/6]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file core_armv8mbl.h.

◆ SCB_SHCSR_NMIACT_Pos [3/6]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 712 of file core_armv8mml.h.

◆ SCB_SHCSR_NMIACT_Pos [4/6]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 539 of file core_cm23.h.

◆ SCB_SHCSR_NMIACT_Pos [5/6]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 712 of file core_cm33.h.

◆ SCB_SHCSR_NMIACT_Pos [6/6]

#define SCB_SHCSR_NMIACT_Pos 5U

SCB SHCSR: NMIACT Position

Definition at line 712 of file core_cm35p.h.

◆ SCB_SHCSR_PENDSVACT_Msk [1/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 713 of file core_armv81mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [2/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Msk [3/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 704 of file core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Msk [4/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 534 of file core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Msk [5/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 535 of file core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Msk [6/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 704 of file core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Msk [7/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 704 of file core_cm35p.h.

◆ SCB_SHCSR_PENDSVACT_Msk [8/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 593 of file core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Msk [9/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 646 of file core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Msk [10/10]

#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)

SCB SHCSR: PENDSVACT Mask

Definition at line 532 of file core_sc300.h.

◆ SCB_SHCSR_PENDSVACT_Pos [1/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 712 of file core_armv81mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [2/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file core_armv8mbl.h.

◆ SCB_SHCSR_PENDSVACT_Pos [3/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 703 of file core_armv8mml.h.

◆ SCB_SHCSR_PENDSVACT_Pos [4/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 533 of file core_cm23.h.

◆ SCB_SHCSR_PENDSVACT_Pos [5/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 534 of file core_cm3.h.

◆ SCB_SHCSR_PENDSVACT_Pos [6/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 703 of file core_cm33.h.

◆ SCB_SHCSR_PENDSVACT_Pos [7/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 703 of file core_cm35p.h.

◆ SCB_SHCSR_PENDSVACT_Pos [8/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 592 of file core_cm4.h.

◆ SCB_SHCSR_PENDSVACT_Pos [9/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 645 of file core_cm7.h.

◆ SCB_SHCSR_PENDSVACT_Pos [10/10]

#define SCB_SHCSR_PENDSVACT_Pos 10U

SCB SHCSR: PENDSVACT Position

Definition at line 531 of file core_sc300.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [1/4]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 725 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [2/4]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 716 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [3/4]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 716 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Msk [4/4]

#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)

SCB SHCSR: SECUREFAULTACT Mask

Definition at line 716 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [1/4]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 724 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [2/4]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 715 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [3/4]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 715 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTACT_Pos [4/4]

#define SCB_SHCSR_SECUREFAULTACT_Pos 4U

SCB SHCSR: SECUREFAULTACT Position

Definition at line 715 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [1/4]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 686 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [2/4]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 677 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [3/4]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 677 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Msk [4/4]

#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)

SCB SHCSR: SECUREFAULTENA Mask

Definition at line 677 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [1/4]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 685 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [2/4]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 676 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [3/4]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 676 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTENA_Pos [4/4]

#define SCB_SHCSR_SECUREFAULTENA_Pos 19U

SCB SHCSR: SECUREFAULTENA Position

Definition at line 676 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [1/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 683 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [2/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 674 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [3/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 674 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Msk [4/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)

SCB SHCSR: SECUREFAULTPENDED Mask

Definition at line 674 of file core_cm35p.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [1/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 682 of file core_armv81mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [2/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 673 of file core_armv8mml.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [3/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 673 of file core_cm33.h.

◆ SCB_SHCSR_SECUREFAULTPENDED_Pos [4/4]

#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U

SCB SHCSR: SECUREFAULTPENDED Position

Definition at line 673 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLACT_Msk [1/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 719 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [2/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Msk [3/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 710 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Msk [4/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 537 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Msk [5/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 541 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Msk [6/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 710 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Msk [7/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 710 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLACT_Msk [8/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 599 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Msk [9/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 652 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Msk [10/10]

#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)

SCB SHCSR: SVCALLACT Mask

Definition at line 538 of file core_sc300.h.

◆ SCB_SHCSR_SVCALLACT_Pos [1/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 718 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [2/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLACT_Pos [3/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 709 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLACT_Pos [4/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 536 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLACT_Pos [5/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 540 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLACT_Pos [6/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 709 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLACT_Pos [7/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 709 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLACT_Pos [8/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 598 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLACT_Pos [9/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 651 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLACT_Pos [10/10]

#define SCB_SHCSR_SVCALLACT_Pos 7U

SCB SHCSR: SVCALLACT Position

Definition at line 537 of file core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [1/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 698 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [2/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [3/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 689 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [4/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [5/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 457 of file core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [6/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 433 of file core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [7/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 528 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [8/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 520 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [9/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 689 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [10/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 689 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [11/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 578 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [12/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 631 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [13/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 445 of file core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Msk [14/14]

#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)

SCB SHCSR: SVCALLPENDED Mask

Definition at line 517 of file core_sc300.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [1/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 697 of file core_armv81mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [2/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file core_armv8mbl.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [3/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 688 of file core_armv8mml.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [4/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file core_cm0.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [5/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 456 of file core_cm0plus.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [6/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 432 of file core_cm1.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [7/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 527 of file core_cm23.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [8/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 519 of file core_cm3.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [9/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 688 of file core_cm33.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [10/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 688 of file core_cm35p.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [11/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 577 of file core_cm4.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [12/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 630 of file core_cm7.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [13/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 444 of file core_sc000.h.

◆ SCB_SHCSR_SVCALLPENDED_Pos [14/14]

#define SCB_SHCSR_SVCALLPENDED_Pos 15U

SCB SHCSR: SVCALLPENDED Position

Definition at line 516 of file core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [1/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 710 of file core_armv81mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [2/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [3/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 701 of file core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [4/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 531 of file core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [5/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 532 of file core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [6/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 701 of file core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [7/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 701 of file core_cm35p.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [8/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 590 of file core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [9/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 643 of file core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Msk [10/10]

#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)

SCB SHCSR: SYSTICKACT Mask

Definition at line 529 of file core_sc300.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [1/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 709 of file core_armv81mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [2/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file core_armv8mbl.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [3/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 700 of file core_armv8mml.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [4/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 530 of file core_cm23.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [5/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 531 of file core_cm3.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [6/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 700 of file core_cm33.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [7/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 700 of file core_cm35p.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [8/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 589 of file core_cm4.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [9/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 642 of file core_cm7.h.

◆ SCB_SHCSR_SYSTICKACT_Pos [10/10]

#define SCB_SHCSR_SYSTICKACT_Pos 11U

SCB SHCSR: SYSTICKACT Position

Definition at line 528 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [1/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 728 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [2/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 719 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [3/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 544 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [4/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 719 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [5/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 719 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [6/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 602 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [7/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 655 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Msk [8/8]

#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)

SCB SHCSR: USGFAULTACT Mask

Definition at line 541 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [1/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 727 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [2/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 718 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [3/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 543 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [4/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 718 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [5/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 718 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [6/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 601 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [7/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 654 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTACT_Pos [8/8]

#define SCB_SHCSR_USGFAULTACT_Pos 3U

SCB SHCSR: USGFAULTACT Position

Definition at line 540 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [1/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 689 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [2/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 680 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [3/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 511 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [4/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 680 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [5/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 680 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [6/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 569 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [7/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 622 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Msk [8/8]

#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)

SCB SHCSR: USGFAULTENA Mask

Definition at line 508 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [1/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 688 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [2/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 679 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [3/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 510 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [4/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 679 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [5/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 679 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [6/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 568 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [7/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 621 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTENA_Pos [8/8]

#define SCB_SHCSR_USGFAULTENA_Pos 18U

SCB SHCSR: USGFAULTENA Position

Definition at line 507 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [1/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 707 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [2/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 698 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [3/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 529 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [4/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 698 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [5/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 698 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [6/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 587 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [7/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 640 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Msk [8/8]

#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)

SCB SHCSR: USGFAULTPENDED Mask

Definition at line 526 of file core_sc300.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [1/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 706 of file core_armv81mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [2/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 697 of file core_armv8mml.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [3/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 528 of file core_cm3.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [4/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 697 of file core_cm33.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [5/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 697 of file core_cm35p.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [6/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 586 of file core_cm4.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [7/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 639 of file core_cm7.h.

◆ SCB_SHCSR_USGFAULTPENDED_Pos [8/8]

#define SCB_SHCSR_USGFAULTPENDED_Pos 12U

SCB SHCSR: USGFAULTPENDED Position

Definition at line 525 of file core_sc300.h.

◆ SCB_STIR_INTID_Msk [1/5]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 902 of file core_armv81mml.h.

◆ SCB_STIR_INTID_Msk [2/5]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 893 of file core_armv8mml.h.

◆ SCB_STIR_INTID_Msk [3/5]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 893 of file core_cm33.h.

◆ SCB_STIR_INTID_Msk [4/5]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 893 of file core_cm35p.h.

◆ SCB_STIR_INTID_Msk [5/5]

#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)

SCB STIR: INTID Mask

Definition at line 813 of file core_cm7.h.

◆ SCB_STIR_INTID_Pos [1/5]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 901 of file core_armv81mml.h.

◆ SCB_STIR_INTID_Pos [2/5]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 892 of file core_armv8mml.h.

◆ SCB_STIR_INTID_Pos [3/5]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 892 of file core_cm33.h.

◆ SCB_STIR_INTID_Pos [4/5]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 892 of file core_cm35p.h.

◆ SCB_STIR_INTID_Pos [5/5]

#define SCB_STIR_INTID_Pos 0U

SCB STIR: INTID Position

Definition at line 812 of file core_cm7.h.

◆ SCB_VTOR_TBLBASE_Msk

#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)

SCB VTOR: TBLBASE Mask

Definition at line 450 of file core_sc300.h.

◆ SCB_VTOR_TBLBASE_Pos

#define SCB_VTOR_TBLBASE_Pos 29U

SCB VTOR: TBLBASE Position

Definition at line 449 of file core_sc300.h.

◆ SCB_VTOR_TBLOFF_Msk [1/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 610 of file core_armv81mml.h.

◆ SCB_VTOR_TBLOFF_Msk [2/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 601 of file core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Msk [3/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 455 of file core_cm3.h.

◆ SCB_VTOR_TBLOFF_Msk [4/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 601 of file core_cm33.h.

◆ SCB_VTOR_TBLOFF_Msk [5/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 601 of file core_cm35p.h.

◆ SCB_VTOR_TBLOFF_Msk [6/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 514 of file core_cm4.h.

◆ SCB_VTOR_TBLOFF_Msk [7/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 558 of file core_cm7.h.

◆ SCB_VTOR_TBLOFF_Msk [8/9]

#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 408 of file core_sc000.h.

◆ SCB_VTOR_TBLOFF_Msk [9/9]

#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)

SCB VTOR: TBLOFF Mask

Definition at line 453 of file core_sc300.h.

◆ SCB_VTOR_TBLOFF_Pos [1/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 609 of file core_armv81mml.h.

◆ SCB_VTOR_TBLOFF_Pos [2/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 600 of file core_armv8mml.h.

◆ SCB_VTOR_TBLOFF_Pos [3/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 454 of file core_cm3.h.

◆ SCB_VTOR_TBLOFF_Pos [4/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 600 of file core_cm33.h.

◆ SCB_VTOR_TBLOFF_Pos [5/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 600 of file core_cm35p.h.

◆ SCB_VTOR_TBLOFF_Pos [6/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 513 of file core_cm4.h.

◆ SCB_VTOR_TBLOFF_Pos [7/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 557 of file core_cm7.h.

◆ SCB_VTOR_TBLOFF_Pos [8/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 407 of file core_sc000.h.

◆ SCB_VTOR_TBLOFF_Pos [9/9]

#define SCB_VTOR_TBLOFF_Pos 7U

SCB VTOR: TBLOFF Position

Definition at line 452 of file core_sc300.h.

◆ SCnSCB [1/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 2043 of file core_armv81mml.h.

◆ SCnSCB [2/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 1887 of file core_armv8mml.h.

◆ SCnSCB [3/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 565 of file core_cm1.h.

◆ SCnSCB [4/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 1384 of file core_cm3.h.

◆ SCnSCB [5/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 1962 of file core_cm33.h.

◆ SCnSCB [6/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 1962 of file core_cm35p.h.

◆ SCnSCB [7/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 1554 of file core_cm4.h.

◆ SCnSCB [8/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 1777 of file core_cm7.h.

◆ SCnSCB [9/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 662 of file core_sc000.h.

◆ SCnSCB [10/10]

#define SCnSCB ((SCnSCB_Type *) SCS_BASE )

System control Register not in SCB

Definition at line 1367 of file core_sc300.h.

◆ SCnSCB_ACTLR_DISDEFWBUF_Msk [1/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

ACTLR: DISDEFWBUF Mask

Definition at line 741 of file core_cm4.h.

◆ SCnSCB_ACTLR_DISDEFWBUF_Msk [2/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)

ACTLR: DISDEFWBUF Mask

Definition at line 668 of file core_sc300.h.

◆ SCnSCB_ACTLR_DISDEFWBUF_Pos [1/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

ACTLR: DISDEFWBUF Position

Definition at line 740 of file core_cm4.h.

◆ SCnSCB_ACTLR_DISDEFWBUF_Pos [2/2]

#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U

ACTLR: DISDEFWBUF Position

Definition at line 667 of file core_sc300.h.

◆ SCnSCB_ACTLR_DISFOLD_Msk [1/3]

#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

Definition at line 738 of file core_cm4.h.

◆ SCnSCB_ACTLR_DISFOLD_Msk [2/3]

#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

Definition at line 961 of file core_cm7.h.

◆ SCnSCB_ACTLR_DISFOLD_Msk [3/3]

#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)

ACTLR: DISFOLD Mask

Definition at line 665 of file core_sc300.h.

◆ SCnSCB_ACTLR_DISFOLD_Pos [1/3]

#define SCnSCB_ACTLR_DISFOLD_Pos 2U

ACTLR: DISFOLD Position

Definition at line 737 of file core_cm4.h.

◆ SCnSCB_ACTLR_DISFOLD_Pos [2/3]

#define SCnSCB_ACTLR_DISFOLD_Pos 2U

ACTLR: DISFOLD Position

Definition at line 960 of file core_cm7.h.

◆ SCnSCB_ACTLR_DISFOLD_Pos [3/3]

#define SCnSCB_ACTLR_DISFOLD_Pos 2U

ACTLR: DISFOLD Position

Definition at line 664 of file core_sc300.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [1/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

Definition at line 744 of file core_cm4.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [2/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

Definition at line 964 of file core_cm7.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [3/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

Definition at line 468 of file core_sc000.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Msk [4/4]

#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)

ACTLR: DISMCYCINT Mask

Definition at line 671 of file core_sc300.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [1/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

Definition at line 743 of file core_cm4.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [2/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

Definition at line 963 of file core_cm7.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [3/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

Definition at line 467 of file core_sc000.h.

◆ SCnSCB_ACTLR_DISMCYCINT_Pos [4/4]

#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U

ACTLR: DISMCYCINT Position

Definition at line 670 of file core_sc300.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [1/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 1020 of file core_armv81mml.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [2/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 939 of file core_armv8mml.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [3/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 668 of file core_cm3.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [4/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 939 of file core_cm33.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [5/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 939 of file core_cm35p.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [6/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 728 of file core_cm4.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [7/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 930 of file core_cm7.h.

◆ SCnSCB_ICTR_INTLINESNUM_Msk [8/8]

#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)

ICTR: INTLINESNUM Mask

Definition at line 661 of file core_sc300.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [1/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 1019 of file core_armv81mml.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [2/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 938 of file core_armv8mml.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [3/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 667 of file core_cm3.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [4/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 938 of file core_cm33.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [5/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 938 of file core_cm35p.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [6/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 727 of file core_cm4.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [7/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 929 of file core_cm7.h.

◆ SCnSCB_ICTR_INTLINESNUM_Pos [8/8]

#define SCnSCB_ICTR_INTLINESNUM_Pos 0U

ICTR: INTLINESNUM Position

Definition at line 660 of file core_sc300.h.

◆ SCS_BASE [1/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 2034 of file core_armv81mml.h.

◆ SCS_BASE [2/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1113 of file core_armv8mbl.h.

◆ SCS_BASE [3/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1878 of file core_armv8mml.h.

◆ SCS_BASE [4/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 534 of file core_cm0.h.

◆ SCS_BASE [5/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 648 of file core_cm0plus.h.

◆ SCS_BASE [6/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 560 of file core_cm1.h.

◆ SCS_BASE [7/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1188 of file core_cm23.h.

◆ SCS_BASE [8/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1375 of file core_cm3.h.

◆ SCS_BASE [9/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1953 of file core_cm33.h.

◆ SCS_BASE [10/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1953 of file core_cm35p.h.

◆ SCS_BASE [11/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1545 of file core_cm4.h.

◆ SCS_BASE [12/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1768 of file core_cm7.h.

◆ SCS_BASE [13/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 657 of file core_sc000.h.

◆ SCS_BASE [14/14]

#define SCS_BASE (0xE000E000UL)

System Control Space Base Address

Definition at line 1358 of file core_sc300.h.

◆ SysTick [1/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 2045 of file core_armv81mml.h.

◆ SysTick [2/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1123 of file core_armv8mbl.h.

◆ SysTick [3/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1889 of file core_armv8mml.h.

◆ SysTick [4/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 540 of file core_cm0.h.

◆ SysTick [5/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 654 of file core_cm0plus.h.

◆ SysTick [6/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 567 of file core_cm1.h.

◆ SysTick [7/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1198 of file core_cm23.h.

◆ SysTick [8/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1386 of file core_cm3.h.

◆ SysTick [9/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1964 of file core_cm33.h.

◆ SysTick [10/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1964 of file core_cm35p.h.

◆ SysTick [11/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1556 of file core_cm4.h.

◆ SysTick [12/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1779 of file core_cm7.h.

◆ SysTick [13/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 664 of file core_sc000.h.

◆ SysTick [14/14]

#define SysTick ((SysTick_Type *) SysTick_BASE )

SysTick configuration struct

Definition at line 1369 of file core_sc300.h.

◆ SysTick_BASE [1/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 2039 of file core_armv81mml.h.

◆ SysTick_BASE [2/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1117 of file core_armv8mbl.h.

◆ SysTick_BASE [3/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1883 of file core_armv8mml.h.

◆ SysTick_BASE [4/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 535 of file core_cm0.h.

◆ SysTick_BASE [5/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 649 of file core_cm0plus.h.

◆ SysTick_BASE [6/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 561 of file core_cm1.h.

◆ SysTick_BASE [7/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1192 of file core_cm23.h.

◆ SysTick_BASE [8/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1380 of file core_cm3.h.

◆ SysTick_BASE [9/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1958 of file core_cm33.h.

◆ SysTick_BASE [10/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1958 of file core_cm35p.h.

◆ SysTick_BASE [11/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1550 of file core_cm4.h.

◆ SysTick_BASE [12/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1773 of file core_cm7.h.

◆ SysTick_BASE [13/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 658 of file core_sc000.h.

◆ SysTick_BASE [14/14]

#define SysTick_BASE (SCS_BASE + 0x0010UL)

SysTick Base Address

Definition at line 1363 of file core_sc300.h.

◆ SysTick_CALIB_NOREF_Msk [1/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 1066 of file core_armv81mml.h.

◆ SysTick_CALIB_NOREF_Msk [2/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 589 of file core_armv8mbl.h.

◆ SysTick_CALIB_NOREF_Msk [3/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 985 of file core_armv8mml.h.

◆ SysTick_CALIB_NOREF_Msk [4/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 479 of file core_cm0.h.

◆ SysTick_CALIB_NOREF_Msk [5/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 503 of file core_cm0plus.h.

◆ SysTick_CALIB_NOREF_Msk [6/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 505 of file core_cm1.h.

◆ SysTick_CALIB_NOREF_Msk [7/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 589 of file core_cm23.h.

◆ SysTick_CALIB_NOREF_Msk [8/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 732 of file core_cm3.h.

◆ SysTick_CALIB_NOREF_Msk [9/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 985 of file core_cm33.h.

◆ SysTick_CALIB_NOREF_Msk [10/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 985 of file core_cm35p.h.

◆ SysTick_CALIB_NOREF_Msk [11/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 790 of file core_cm4.h.

◆ SysTick_CALIB_NOREF_Msk [12/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 1010 of file core_cm7.h.

◆ SysTick_CALIB_NOREF_Msk [13/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 514 of file core_sc000.h.

◆ SysTick_CALIB_NOREF_Msk [14/14]

#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)

SysTick CALIB: NOREF Mask

Definition at line 717 of file core_sc300.h.

◆ SysTick_CALIB_NOREF_Pos [1/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 1065 of file core_armv81mml.h.

◆ SysTick_CALIB_NOREF_Pos [2/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 588 of file core_armv8mbl.h.

◆ SysTick_CALIB_NOREF_Pos [3/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 984 of file core_armv8mml.h.

◆ SysTick_CALIB_NOREF_Pos [4/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 478 of file core_cm0.h.

◆ SysTick_CALIB_NOREF_Pos [5/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 502 of file core_cm0plus.h.

◆ SysTick_CALIB_NOREF_Pos [6/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 504 of file core_cm1.h.

◆ SysTick_CALIB_NOREF_Pos [7/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 588 of file core_cm23.h.

◆ SysTick_CALIB_NOREF_Pos [8/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 731 of file core_cm3.h.

◆ SysTick_CALIB_NOREF_Pos [9/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 984 of file core_cm33.h.

◆ SysTick_CALIB_NOREF_Pos [10/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 984 of file core_cm35p.h.

◆ SysTick_CALIB_NOREF_Pos [11/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 789 of file core_cm4.h.

◆ SysTick_CALIB_NOREF_Pos [12/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 1009 of file core_cm7.h.

◆ SysTick_CALIB_NOREF_Pos [13/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 513 of file core_sc000.h.

◆ SysTick_CALIB_NOREF_Pos [14/14]

#define SysTick_CALIB_NOREF_Pos 31U

SysTick CALIB: NOREF Position

Definition at line 716 of file core_sc300.h.

◆ SysTick_CALIB_SKEW_Msk [1/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 1069 of file core_armv81mml.h.

◆ SysTick_CALIB_SKEW_Msk [2/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 592 of file core_armv8mbl.h.

◆ SysTick_CALIB_SKEW_Msk [3/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 988 of file core_armv8mml.h.

◆ SysTick_CALIB_SKEW_Msk [4/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 482 of file core_cm0.h.

◆ SysTick_CALIB_SKEW_Msk [5/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 506 of file core_cm0plus.h.

◆ SysTick_CALIB_SKEW_Msk [6/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 508 of file core_cm1.h.

◆ SysTick_CALIB_SKEW_Msk [7/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 592 of file core_cm23.h.

◆ SysTick_CALIB_SKEW_Msk [8/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 735 of file core_cm3.h.

◆ SysTick_CALIB_SKEW_Msk [9/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 988 of file core_cm33.h.

◆ SysTick_CALIB_SKEW_Msk [10/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 988 of file core_cm35p.h.

◆ SysTick_CALIB_SKEW_Msk [11/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 793 of file core_cm4.h.

◆ SysTick_CALIB_SKEW_Msk [12/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 1013 of file core_cm7.h.

◆ SysTick_CALIB_SKEW_Msk [13/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 517 of file core_sc000.h.

◆ SysTick_CALIB_SKEW_Msk [14/14]

#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)

SysTick CALIB: SKEW Mask

Definition at line 720 of file core_sc300.h.

◆ SysTick_CALIB_SKEW_Pos [1/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 1068 of file core_armv81mml.h.

◆ SysTick_CALIB_SKEW_Pos [2/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 591 of file core_armv8mbl.h.

◆ SysTick_CALIB_SKEW_Pos [3/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 987 of file core_armv8mml.h.

◆ SysTick_CALIB_SKEW_Pos [4/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 481 of file core_cm0.h.

◆ SysTick_CALIB_SKEW_Pos [5/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 505 of file core_cm0plus.h.

◆ SysTick_CALIB_SKEW_Pos [6/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 507 of file core_cm1.h.

◆ SysTick_CALIB_SKEW_Pos [7/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 591 of file core_cm23.h.

◆ SysTick_CALIB_SKEW_Pos [8/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 734 of file core_cm3.h.

◆ SysTick_CALIB_SKEW_Pos [9/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 987 of file core_cm33.h.

◆ SysTick_CALIB_SKEW_Pos [10/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 987 of file core_cm35p.h.

◆ SysTick_CALIB_SKEW_Pos [11/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 792 of file core_cm4.h.

◆ SysTick_CALIB_SKEW_Pos [12/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 1012 of file core_cm7.h.

◆ SysTick_CALIB_SKEW_Pos [13/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 516 of file core_sc000.h.

◆ SysTick_CALIB_SKEW_Pos [14/14]

#define SysTick_CALIB_SKEW_Pos 30U

SysTick CALIB: SKEW Position

Definition at line 719 of file core_sc300.h.

◆ SysTick_CALIB_TENMS_Msk [1/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 1072 of file core_armv81mml.h.

◆ SysTick_CALIB_TENMS_Msk [2/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 595 of file core_armv8mbl.h.

◆ SysTick_CALIB_TENMS_Msk [3/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 991 of file core_armv8mml.h.

◆ SysTick_CALIB_TENMS_Msk [4/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 485 of file core_cm0.h.

◆ SysTick_CALIB_TENMS_Msk [5/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 509 of file core_cm0plus.h.

◆ SysTick_CALIB_TENMS_Msk [6/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 511 of file core_cm1.h.

◆ SysTick_CALIB_TENMS_Msk [7/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 595 of file core_cm23.h.

◆ SysTick_CALIB_TENMS_Msk [8/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 738 of file core_cm3.h.

◆ SysTick_CALIB_TENMS_Msk [9/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 991 of file core_cm33.h.

◆ SysTick_CALIB_TENMS_Msk [10/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 991 of file core_cm35p.h.

◆ SysTick_CALIB_TENMS_Msk [11/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 796 of file core_cm4.h.

◆ SysTick_CALIB_TENMS_Msk [12/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 1016 of file core_cm7.h.

◆ SysTick_CALIB_TENMS_Msk [13/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 520 of file core_sc000.h.

◆ SysTick_CALIB_TENMS_Msk [14/14]

#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)

SysTick CALIB: TENMS Mask

Definition at line 723 of file core_sc300.h.

◆ SysTick_CALIB_TENMS_Pos [1/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 1071 of file core_armv81mml.h.

◆ SysTick_CALIB_TENMS_Pos [2/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 594 of file core_armv8mbl.h.

◆ SysTick_CALIB_TENMS_Pos [3/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 990 of file core_armv8mml.h.

◆ SysTick_CALIB_TENMS_Pos [4/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 484 of file core_cm0.h.

◆ SysTick_CALIB_TENMS_Pos [5/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 508 of file core_cm0plus.h.

◆ SysTick_CALIB_TENMS_Pos [6/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 510 of file core_cm1.h.

◆ SysTick_CALIB_TENMS_Pos [7/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 594 of file core_cm23.h.

◆ SysTick_CALIB_TENMS_Pos [8/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 737 of file core_cm3.h.

◆ SysTick_CALIB_TENMS_Pos [9/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 990 of file core_cm33.h.

◆ SysTick_CALIB_TENMS_Pos [10/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 990 of file core_cm35p.h.

◆ SysTick_CALIB_TENMS_Pos [11/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 795 of file core_cm4.h.

◆ SysTick_CALIB_TENMS_Pos [12/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 1015 of file core_cm7.h.

◆ SysTick_CALIB_TENMS_Pos [13/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 519 of file core_sc000.h.

◆ SysTick_CALIB_TENMS_Pos [14/14]

#define SysTick_CALIB_TENMS_Pos 0U

SysTick CALIB: TENMS Position

Definition at line 722 of file core_sc300.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [1/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 1048 of file core_armv81mml.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [2/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 571 of file core_armv8mbl.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [3/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 967 of file core_armv8mml.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [4/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 461 of file core_cm0.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [5/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 485 of file core_cm0plus.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [6/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 487 of file core_cm1.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [7/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 571 of file core_cm23.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [8/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 714 of file core_cm3.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [9/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 967 of file core_cm33.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [10/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 967 of file core_cm35p.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [11/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 772 of file core_cm4.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [12/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 992 of file core_cm7.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [13/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 496 of file core_sc000.h.

◆ SysTick_CTRL_CLKSOURCE_Msk [14/14]

#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)

SysTick CTRL: CLKSOURCE Mask

Definition at line 699 of file core_sc300.h.